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Subject:	Seeking design information on PWB conductor spacing for high voltage (500-1000 VDC) applications
From:	Gerald Bogert <[log in to unmask]>
Reply To:	TechNet E-Mail Forum <[log in to unmask]>, Gerald Bogert <[log in to unmask]>
Date:	Thu, 16 Aug 2007 18:24:14 -0400
Content-Type:	text/plain
Parts/Attachments:	text/plain (51 lines)

August 16, 2007

IPC-2221 section 6.3 and the associated table provides specific electrical
conductor spacing requirements for voltages up to 500 volts. However, for
voltages > 500 volts, it defaults to a formula in section 6.3.

What is the technical basis for the minimum spacing requirements that are
listed in the table? How reliable is the formula for voltages > 500 volts.
How valid is the formula if we have 1000 VDC on the PWB?

Since the table does not specifically list minimum electrical spacing for
voltages > 500 volts is the formula just a “SWAG” or based on real data? If
so, what is the formula based on?

Does anyone have design standards for high voltage PWB spacings that they
are willing to share?

We had an OEM that had recent field failures (shorts to internal traces) of
a conformal coated multilayer FR4 PWB (0.062 in) that has both low (logic
voltage) and high (approx 780 VDC nominal) circuits. The board was required
to be designed to IPC-D-275 requirements, and the table in 275 is basically
the same as in IPC-2221.

The PWB is being redesigned and I need to verify the new design meets
reliable and valid minimum conductor spacing requirements. Are there any
design standards other than IPC-2221 that could be used for high voltage
PWB?

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