Subject: | |
From: | |
Reply To: | (Designers Council Forum) |
Date: | Wed, 29 Aug 2007 13:56:32 -0700 |
Content-Type: | text/plain |
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Hey, are y'all gonna offer shuttle service from/to the convention center
for any of us out-of-town folks at the Cadence User Conference? :)
--
George Patrick
Tektronix, Inc.
Central Engineering, EDS Applications Support
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
* 503-627-5272 (voice) * 503-627-5587 (fax)
http://www.tektronix.com http://www.pcb-designer.com
"Off-Grid and Proud of it!"
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
Silicon Valley Chapter - IPC
Sent: Wednesday, August 29, 2007 13:35
To: [log in to unmask]
Subject: [DC] Meeting Announcement: Silicon Valley Chapter (Sep. 11,
2007)
IPC Designers Council - Silicon Valley Chapter
Tuesday, Sept 11th, 2007
Time: 11:30AM - 1:30PM
Mentor Graphics
1001 Ridder Park Drive, San Jose, CA
Speaker: Mike Wilson (ADI / Cadplex Sales)
Topic: Tools for mixed EDA flows ( Cadence and Mentor )
Schematic symbol generation tool
Converting symbols
FPGA Bback-Annotation
Engineer FloorPlanning prior to PCB layout
Cross-probe from schematic to board
Accelerated Placement techniques
Design Re-Use modules for flat schematics
FPGA / Board Co-Design
Please RSVP to: [log in to unmask]
$1 for members; $5 for guests
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To temporarily stop/(restart) delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL/(MAIL)
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
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