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July 2007

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Subject:
From:
"Whittaker, Dewey (EHCOE)" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Whittaker, Dewey (EHCOE)
Date:
Mon, 30 Jul 2007 12:12:22 -0700
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text/plain (317 lines)
So I guess that includes the hole world also? I don't disagree that if
you have control over everything (chemistries, materials, design,
processes, function, and end use) you could make those decisions, but
for long term reliability with the trend toward continued outsourcing, I
stand by my responses.
Dewey


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Dwight Mattix
Sent: Monday, July 30, 2007 11:03 AM
To: [log in to unmask]
Subject: Re: [TN] Via tenting

re: 4 suggestions mentioned earlier
<Phil Bavaro is the master of the universe in this area>

1) via tenting top side only
As I understand your description this in not what you want to do. This
may 
be a planarity problem, no? Although you don't have to worry about the
vias 
venting into your solder joint.

2) via tenting bottom side only
Bad idea. Been there, done that.  Take it to the bank, this will give
you 
solder voids. Via won't be completely filled by s/m but will block the 
entrapped gasses from venting to backside.

3) via plugging from the bottom side
Full plugging is as a nearly an ideal condition as you can hope for. We
do 
a lot of this with great success. Not all fabs have the recipe yet.
If anything, preferred filling is from topside (with post
planarization). 
 From either side OK as long as it's filled to top surface and planar at

the top (solder) surface to minimize venting/voiding problems into the 
solder joint

4) via encroached
If by "via encroached" you mean encroaching on the via with soldermask
on 
the backside;
Then, yes we've done this a lot. This is arguably "the elegant"
solution.

It allows solder venting through the via, thus minimizing voiding.
If pwb supplier uses s/m "tent breaker" approach(s/m aperture = drill
minus 
a few mil) then usually the via wets partially but solder never comes to

back sider surface.
If pwb supplier uses a "cheater via" approach (s/m aperture = drill plus
a 
few mil) then the via may substantially fill w/ solder but not come to
the 
surface. There isn't enough annular ring on the back side to allow
solder 
to wet and hold on a miniscus on the surface ring. Surface tension holds

the solder back into the via.]

5) None of the above:
If thru via drill is small (on order of 10 mils) resulting in an even 
smaller finished via then just leave via open. It'll vent and not wet 
through to other side.
Phil and I did a lot of this with great success. Not always the
politically 
expedient thing to do. Someone will push back in review cycle, not 
understanding how it works or believing our empirical evidence of
success. 
In those cases we'd use method 3 or 4 (above) as a concession to their
"If 
there are any problems then the blood will be on your hands" threats.






At 09:17 AM 7/30/2007, Hogg, Blair K. wrote:
>If the via is in a pad, or a heatsink area under a device which is not
>normally covered with soldermask, would you put soldermask over just
the
>via?
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Whittaker, Dewey
>(EHCOE)
>Sent: Monday, July 30, 2007 10:28 AM
>To: [log in to unmask]
>Subject: Re: [TN] Via tenting
>
>I'll spare you the tribal knowledge of dual dwellings, but if long term
>reliability is a requirement choose one of the following:
>
>*         A plated-over filled via using Taiyo or Peter's material(
>CB100 need not apply)
>
>*         A tented via where both sides are capped and covered with a
>SMOBC per IPC-SM-840
>
>
>
>Dewey
>
>
>
>-----Original Message-----
>
>From: TechNet [mailto:[log in to unmask]] On Behalf Of West, Jim
>
>Sent: Friday, July 27, 2007 12:52 PM
>
>To: [log in to unmask]
>
>Subject: [TN] Via tenting
>
>
>
>Hi,
>
>
>
>We have an application where we are using a QFN/SON package that has
one
>
>large exposed pad at the bottom of the package.  In order to ensure
good
>
>electrical characteristics and thermal protection, the chip
manufacturer
>
>recommends a thermal pad via design.  The recommendation is to use 6
>
>via's within the large pad placed on a 1.0mm pitch to help facilitate
>
>the thermal relief.  In addition, they suggest 0.3mm diameter drill
>
>holes.  There are several suggestions on what one would do to these
>
>via's to reduce the exposure of excess voiding during the reflow
>
>process.  One suggestion is via tenting top side only, second
suggestion
>
>is via tenting bottom side only, third suggestion is via plugging from
>
>the bottom side, and finally the fourth suggestion is via encroached
>
>from the bottom.
>
>
>
>As I look at these suggestions,  I would probably utilize the via
>
>tenting top side only, since this would probably result in smaller
>
>voids, but one of the risks is a hindrance of proper paste printing.
>
>Options 2 and 3, I would think that there would be an increased in out
>
>gassing and voiding.  The fourth option would cause reduced voiding,
but
>
>could cause a lower standoff of the package, causing improper soldering
>
>conditions.
>
>
>
>
>
>Anyone have a thoughts/experience on how to handle this type of
>
>application?
>
>
>
>Best Regards,
>
>
>
>
>
>
>
>Jim West
>
>Engineering Manager
>
>Nexergy Inc.
>
>www.nexergy.com
>
>tel: (614) 351-6216
>
>fax: (614) 324-1979
>
>
>
>
>
>
>
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