I'll spare you the tribal knowledge of dual dwellings, but if long term
reliability is a requirement choose one of the following:
* A plated-over filled via using Taiyo or Peter's material(
CB100 need not apply)
* A tented via where both sides are capped and covered with a
SMOBC per IPC-SM-840
Dewey
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of West, Jim
Sent: Friday, July 27, 2007 12:52 PM
To: [log in to unmask]
Subject: [TN] Via tenting
Hi,
We have an application where we are using a QFN/SON package that has one
large exposed pad at the bottom of the package. In order to ensure good
electrical characteristics and thermal protection, the chip manufacturer
recommends a thermal pad via design. The recommendation is to use 6
via's within the large pad placed on a 1.0mm pitch to help facilitate
the thermal relief. In addition, they suggest 0.3mm diameter drill
holes. There are several suggestions on what one would do to these
via's to reduce the exposure of excess voiding during the reflow
process. One suggestion is via tenting top side only, second suggestion
is via tenting bottom side only, third suggestion is via plugging from
the bottom side, and finally the fourth suggestion is via encroached
from the bottom.
As I look at these suggestions, I would probably utilize the via
tenting top side only, since this would probably result in smaller
voids, but one of the risks is a hindrance of proper paste printing.
Options 2 and 3, I would think that there would be an increased in out
gassing and voiding. The fourth option would cause reduced voiding, but
could cause a lower standoff of the package, causing improper soldering
conditions.
Anyone have a thoughts/experience on how to handle this type of
application?
Best Regards,
Jim West
Engineering Manager
Nexergy Inc.
www.nexergy.com
tel: (614) 351-6216
fax: (614) 324-1979
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