Hello Tom,

I have more questions than answers at this time. Is this the first time
that this board failed? Or is this a new product that you build a few
prototypes? What is the FHS that is affected? What is the copper plating
thickness in the vias? What is the peak reflow temperature? How many
layers is the PCB? What is the material in each layer?

I suggest that you contact PWB Interconnect Solutions for their advice.
We used their services to improve our product quality and reliability in
the past. You can find them at the attached link:
http://www.maxdbc.net/pwb/

Hope this helps,
Paymon

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tom Parkinson
Sent: June 5, 2007 10:14 AM
To: [log in to unmask]
Subject: [TN] Via Open

Tech Net & Designer Net

Greetings. We are running into a situation on Lead Free processed PCBs.
Failure mode is finding open vias during unit testing (fully populated).

Boards are Tg170, Material type EM320, 0.063" thick boards.  
6 layers of 1 oz copper. ENIG 3~5u"

Suspect vias go from top layer to bottom layer only.

After running through reflow, we have found vias open. No visual signs
of
delamination, however when ohming out the via, if we press on the via we
get
continuity - thus we suspect the vias are opening during the process.

Anyone out there having these problems, or information concerning this
failure mode?  Z-expansion failure?


Tom Parkinson 
Quality System Manager - CIT
WinTronics, Inc.
Phone: 724-981-5770 - extension 235

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