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June 2007

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Subject:
From:
Lee parker <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Lee parker <[log in to unmask]>
Date:
Tue, 5 Jun 2007 11:11:12 -0400
Content-Type:
text/plain
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text/plain (70 lines)
Tom

This sounds as if the the thickness of the hole wall copper is deficient. I 
would make some cross sections. Many OEMs require representative cross 
sections of the smallest hole be included with each shipment and the check 
on some kind of declining frequency.

Best regards

Lee

J. Lee Parker, Ph.D.
JLP Consultants LLC
804 779 3389


----- Original Message ----- 
From: "Tom Parkinson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, June 05, 2007 10:13 AM
Subject: [TN] Via Open


Tech Net & Designer Net

Greetings. We are running into a situation on Lead Free processed PCBs.
Failure mode is finding open vias during unit testing (fully populated).

Boards are Tg170, Material type EM320, 0.063" thick boards.
6 layers of 1 oz copper. ENIG 3~5u"

Suspect vias go from top layer to bottom layer only.

After running through reflow, we have found vias open. No visual signs of
delamination, however when ohming out the via, if we press on the via we get
continuity - thus we suspect the vias are opening during the process.

Anyone out there having these problems, or information concerning this
failure mode?  Z-expansion failure?


Tom Parkinson
Quality System Manager - CIT
WinTronics, Inc.
Phone: 724-981-5770 - extension 235

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