You need to get some x-sections going.  Might be more conventional plated 
hole wall defects in play.

However, on the subject of EM320.
Are you using EM320 (dicy cured) of EM320LF (phenolic cured for pb free assy)?

There's a big difference in survivability between these two similarly named 
materials.  I strongly recommend use of the EM320LF if you're soldering at 
Pb-free temps.

We've had good luck with EM320LF in several designs we've converted to 
Pb-free in this thickness range..  Designs have ranged from 1mm thick 2+4+2 
stacked uVia to 0.093" single lam plated through hole 10 layer.  They've 
done well through 1000+ cycles (150C) of IST after 3x, 6x, 9x IST 
pre-conditioning at 260C (the uVia design went to 2000 cycles w/out failure).

dw


At 07:13 AM 6/5/2007, Tom Parkinson wrote:
>Tech Net & Designer Net
>
>Greetings. We are running into a situation on Lead Free processed PCBs.
>Failure mode is finding open vias during unit testing (fully populated).
>
>Boards are Tg170, Material type EM320, 0.063" thick boards.
>6 layers of 1 oz copper. ENIG 3~5u"
>
>Suspect vias go from top layer to bottom layer only.
>
>After running through reflow, we have found vias open. No visual signs of
>delamination, however when ohming out the via, if we press on the via we get
>continuity - thus we suspect the vias are opening during the process.
>
>Anyone out there having these problems, or information concerning this
>failure mode?  Z-expansion failure?
>
>
>Tom Parkinson
>Quality System Manager - CIT
>WinTronics, Inc.
>Phone: 724-981-5770 - extension 235
>
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