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May 2007

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Subject:
From:
Richard Kraszewski <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Richard Kraszewski <[log in to unmask]>
Date:
Tue, 29 May 2007 09:47:01 -0500
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I'm pretty sure that the details are presented in IPC-9201, Surface
Insulation, Resistance Handbook

Rich K / GTS
847-621-7310
 
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Upton, Shawn
Sent: Tuesday, May 29, 2007 8:51 AM
To: [log in to unmask]
Subject: [TN] Insulation Resistance

Is there a formula, or rule of thumb, for expected resistance between 2
traces?  That is, for two traces 10mils apart for 1000mils long, expect
as low as x ohms for top/bottom with regular soldermask.  I know the
inner layers are higher resistance, but I'm looking for answers both for
inner and outer layers.

I ask as I'm obviously working on design where I want nice high
resistance, to prevent leakage currents.  Coworker is working on a board
where he made an "oops" and put a 35V supply line 10mils from a high
impedance node (near 0V normally), outer layers, and is getting nearly a
microamp of leakage.  He thinks it's a bad board; but we don't have
actual PCB numbers to say good or not--he's just going to redo the
design.  As I start in some designs with similar issues, I'd rather have
some numbers/formulas, rather than "as much distance as possible".

Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336

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