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May 2007

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Subject:
From:
Werner Engelmaier <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Fri, 11 May 2007 10:51:34 EDT
Content-Type:
text/plain
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text/plain (28 lines)
Hi 'Netters,
I am coming across some horror stories with ENIG plating inside vias, with 
the ENIG fracturing during solder-T excursions and then digging into the ED-Cu 
causing stress concentrations and ED-Cu fracturing. My own fatigue ductility 
testing of ED-Cu foil with ENIG plating shows much reduced fatigue life. This 
is, of course of no consequence on a soldering pad, but inside the via, 
particularly with the much higher solder-T's required for SAC, this turns out to be a 
real problem.
I would appreciate hearing about other experiences, and how people are 
handling this.

Werner



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