Q1: Are the failing net repetitive from one board to another?
Q2: Are any of the failing net part of a timing circuit in which you
could vary the threshold for Pass/Fail criteria.
Q3: What was the PWB yield or can you safely eliminate it.
Q4: What style of probes are you using?
Victor,
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Rojas, Juan
Sent: Tuesday, May 01, 2007 3:06 PM
To: [log in to unmask]
Subject: Re: [TN] LeadFree - ICT FPY Benchmarking
Thanks John,
Yes we are having what it appears to be typical contact problems (due to
residues like: flux, oxidation, etc.) But I can not prove this yet; even
when we re-test a failing board it passes without doing anything to it;
this is not sufficient to convince my fellow process engineer.
We also have a lot of problems with capacitor tests that fails
marginally it is a very unstable test (caps)I attribute it still to
residue but again it is very difficult to me to prove it.
Any ideas? Comments are welcome.
Best regards,
Juan Rojas | Sr. Test Engineer
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of John Burke
Sent: Tuesday, May 01, 2007 3:00 PM
To: [log in to unmask]
Subject: Re: [TN] LeadFree - ICT FPY Benchmarking
Agreed, attention to detail is everything...
Juan, If you are having an issue with yield (which you have not stated)
how
does it compare with the leaded version?
John
John Burke
(408) 515 4992
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D.
Sent: Tuesday, May 01, 2007 12:09 PM
To: [log in to unmask]
Subject: Re: [TN] LeadFree - ICT FPY Benchmarking
Well, thank you. We certainly put a lot of effort into it. It is really
amazing what it takes to get better than 5 sigma.
Everything from pad design library, part type selection, DFMEA, type of
pwb material, surface finish, selection and qualification of solder
paste, process details, component vendor qualification, receiving
inspection procedures, process controls on reflow/paste
print/pickandplace/reflow/wavesolder, fixture DFMEA, etc., etc,.......
When you think about it, all of the efforts put into getting a 99%
cumulative yield and maintaining it over time is a major task. Many are
doing it today, but it sure is not an easy thing to accomplish.
-----Original Message-----
From: Rojas, Juan [mailto:[log in to unmask]]
Sent: Tuesday, May 01, 2007 1:54 PM
To: TechNet E-Mail Forum; Stadem, Richard D.
Subject: RE: [TN] LeadFree - ICT FPY Benchmarking
Wow! you're really doing well.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D.
Sent: Tuesday, May 01, 2007 1:08 PM
To: [log in to unmask]
Subject: Re: [TN] LeadFree - ICT FPY Benchmarking
It should be around 99% or better.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Rojas, Juan
Sent: Tuesday, May 01, 2007 11:36 AM
To: [log in to unmask]
Subject: [TN] LeadFree - ICT FPY Benchmarking
Hi Everyone,
Would you mind if you can share with me what a typical ICT FPY is?
For the following PCBA:
Pb-Free process
~300 Test points
Low Board complexity (~500 analog components)
Board size: 6 x 9 in
Single side board
Test pad size diameter 35 thou
A ball park number would be fine.
Best regards,
Juan Rojas, MITMB | Sr. Test Engineer | Harman/Becker Automotive Systems
| office: (270) 598-4555 | www.harmanbecker.com
<http://www.harmanbecker.com/harmanBecker/www_root/index2.jsp?language=U
S>
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