TGASIA Archives

May 2007

TGAsia@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Condense Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Sender:
X-To:
Asia Committe Task Group Forum <[log in to unmask]>, Johnny Chen <[log in to unmask]>
Date:
Tue, 29 May 2007 09:11:06 +0800
Content-Disposition:
inline
Reply-To:
Asia Committe Task Group Forum <[log in to unmask]>, Jackson Chan <[log in to unmask]>
Content-type:
multipart/mixed; Boundary="0__=C7BBF879DF9663788f9e8a93df938690918cC7BBF879DF966378"
Subject:
From:
Jackson Chan <[log in to unmask]>
X-cc:
In-Reply-To:
MIME-Version:
1.0
Parts/Attachments:
text/plain (3178 bytes) , pic00041.jpg (6 kB)
Dear all,

It is the sidetrack information.  For the chip pad, the presence of the
sufficient clearance (e.g. 75um) can be helpful to reduce the MCB (Mid chip
solder ball) for the paste application. It is the field experience

Regards,

Jackson

Cookson Electronics - Alpha Metals
Technical Services Manager



                                                                           
             Johnny Chen                                                   
             <[log in to unmask]                                             
             LEXTRONICS.COM>                                            To 
             Sent by: TGAsia           [log in to unmask]                      
             <[log in to unmask]>                                           cc 
                                                                           
                                                                   Subject 
             28/05/2007 20:13          [TGA] Solder mask clearance around  
                                       the lands                           
                                                                           
             Please respond to                                             
               Asia Committe                                               
             Task Group Forum                                              
             <[log in to unmask]>;                                             
             Please respond to                                             
                Johnny Chen                                                
             <[log in to unmask]                                             
              LEXTRONICS.COM>                                              
                                                                           
                                                                           




Dear all,

Would you please advise which IPC defines the solder mask clearance around
the lands for NSMD land pattern?

(Embedded image moved to file: pic00041.jpg)

Thanks & best regards,
Johnny
- Process Engineering
Creating Value That Increases Customer Competitiveness


Legal Disclaimer: The information contained in this message may be
privileged and confidential. It is intended to be read only by the
individual or entity to whom it is addressed or by their designee. If the
reader of this message is not the intended recipient, you are on notice
that any distribution of this message, in any form, is strictly prohibited.
If you have received this message in error, please immediately notify the
sender and delete or destroy any copy of this message


                Internet E-mail Confidentiality Disclaimer
  This e-mail message may contain privileged or confidential information.
     If you are not the intended recipient, you may not disclose, use,
 disseminate, distribute, copy or rely upon this message or attachment in
any way.  If you received this e-mail in error, please return by forwarding
 the message and its attachments to the sender. Microtek Laboratories and
its employees and agents do not accept liability for any errors, omissions,
 corruptions or virus in the contents of this message or any attachments.



ATOM RSS1 RSS2