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March 2007

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Subject:
From:
"Stadem, Richard D." <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Stadem, Richard D.
Date:
Sat, 3 Mar 2007 06:38:12 -0600
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text/plain (195 lines)
Ryan, Ramon is talking about filling via-in-pad, not vias that go all
the way through the assembly. 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ryan Grant
Sent: Friday, March 02, 2007 4:18 PM
To: [log in to unmask]
Subject: Re: [TN] Via in Pad question

Ramon, 

What you describe is correct and is the same technique for paste in hole
through hole soldering.  HOWEVER, there is also the tendency for the
solder paste to 'drip' out the bottom side.  This isn't always a problem
if filling the via with solder is the last surface mount soldering
operation.  But if you must print solder on the 'drip' side, the 'drip'
will lift and/or dent the stencil; thus becoming a major issue.

Thanks,
Ryan

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Dehoyos, Ramon
Sent: Wednesday, February 28, 2007 10:37 AM
To: [log in to unmask]
Subject: Re: [TN] Via in Pad question

	For incorrect designs, where the vias are open. Would a bare
board, with sufficient paste on the VIP to fill the vias, reflow run
help? Other issues may pop up, but the vias would be filled.
	Ramon



-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D.
Sent: Tuesday, February 27, 2007 1:44 PM
To: [log in to unmask]
Subject: Re: [TN] Via in Pad question

You just described the correct way to do it. 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Marsico, James
Sent: Tuesday, February 27, 2007 12:14 PM
To: [log in to unmask]
Subject: Re: [TN] Via in Pad question

We've been using vias in pads for over 20 years.  The vias are filled
with resin, then the filled via is metalized and copper plated along
with the pad.  The result is what appears to be a solid pad.

Jim Marsico
EDO Corporation
Amityville:  631-630-5079
Bohemia:  631-218-7057
[log in to unmask]

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Whittaker, Dewey
(EHCOE)
Sent: Tuesday, February 27, 2007 1:04 PM
To: [log in to unmask]
Subject: Re: [TN] Via in Pad question

Avoid them if it's possible, if not have a good via protection process
and communicate with your contract manufacturer. He needs to be aware of
whether he has to deal with open holes or depressions so he can
compensate with paste application.
Dewey

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Carl VanWormer
Sent: Tuesday, February 27, 2007 9:58 AM
To: [log in to unmask]
Subject: [TN] Via in Pad question

I am looking for guidance on using vias in pads of surface mount
components.  The concept is great for high speed design, since it gives
the least inductance for mounting bypass caps.  It sounds easy, but I'm
sure there are some pitfalls and there may be some rules I will break.
Any guidance towards documents on this combination would be appreciated.
Also, any stories to scare me away from this approach will be fun to
hear.

Later,
Carl





Carl Van Wormer
Cipher Systems
1800 NW 169th Place, Suite B-100
Beaverton, OR  97006
Phone (503)-617-7447 extension 20    

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