The flip-flop lay-out has a draw back for the board manufacturer, that is
the need to silk screen the back print (legend or components identification)
twice even if the board has it on one side only. This would be even worse if
the board has also tented vias on one side only, again this has to be
screened twice. This would add two steps to the bare board manufacturing and
would require two additional thermal excursion to cure the legend ink and
the tenting solder mask.
Sherif Refaat.
Technology Roadmap Consultants Inc.
----- Original Message -----
From: "Stadem, Richard D." <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, March 02, 2007 3:58 PM
Subject: Re: [TN] Flip-flop panels
I have been flip-flopping for years (I showed John Kerry how to do it),
and I originally put this method on the forum three years ago.
I added a note in my original posting at that time to address the
specific issues you mentioned about uneven layer stackup, or other
reasons; if you cannot do it as part of the panel, then use a durostone
carrier through print, place, reflow, and wash (if used). Then simply
run the fixtures back through the line after turning the panels over,
one up, one down. This way you do not have to do the up/down
configuration on the pwb panel if there are problems, as you noted. You
still get to complete both sides of the pwb in a single set-up, putting
two images on a single stencil saves the cost of a stencil, and you can
utilize all of the machine feeder capacity.
Then the only limitation when using this method is having parts with too
high of a mass to be able to stay on the pwb upside down during
secondary reflow. And guess what? I have a fix for that too! If there
are only one or two or maybe three high-mass parts (large BGAs for
example), then I ask the customer if it is permissible to epoxy the four
corners of the BGA using SMT epoxy after the first pass through the
oven. It does not hurt the reliability, and you can still cut the cost
out of the process.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Frank Kimmey
Sent: Friday, March 02, 2007 1:32 PM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels
Ioan,
You've listed the biggest of the Pros here, but could also add the
evener distribution of coppers (less warping).
Unfortunately it looks like from the impedance requirements you listed
this particular design will not work well with flip-flop panelizing.
You need to have matched impedance layer for layer if you want to flip
flop and you will need to assure the distance between layers is
consistent top to bottom (symmetrical stackup).
The Design you describe might work, but sounds a little risky and
probably should be experimented with prior to taking to volume.
Flip-flop panelization usually works best with the simpler boards that
have a low enough part count to load in a single pass.
I don't know how comfortable I would be if I found out my CM was doing
flip-flop with my controller impedance designs (most of my multilayers
are asymmetrical due to design requirements).
Hope it helps,
FNK
Frank N Kimmey CID+
Principal PCB Designer
PCB Programs
Powerwave Technologies Inc
Office 916-941-3159
Fax 916-941-3195
Mobile 916-670-0645
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tempea, Ioan
Sent: Friday, March 02, 2007 11:16 AM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels
John,
Steve is right on the money. Best solution for JIT, one piece flow. When
the mechanical-test-packing cell is almost out of boards, you just flip
the boards half assembled, with no down time for changeover, and start
supplying again.
Regards,
Ioan
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Steve Gregory
Sent: Friday, March 02, 2007 2:09 PM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels
Hi John,
I've built panels that had flip-flopped boards before, (small narrow
double-sided SMT boards for a bar code reader pen), and it made things
so easy. One stencil, one SMT set-up, to do both sides of the panel on
one line.
After they come out of the reflow oven from the first side (and they've
cooled down of course), you just stick them right back in the screen
printer for the other side without so much as missing a beat...pretty
cool, eh?
-Steve Gregory-
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of John Parsons
Sent: Friday, March 02, 2007 12:51 PM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels
Ioan,
Why would you want to design an array like this?
John Parsons
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tempea, Ioan
Sent: Friday, March 02, 2007 10:23 AM
To: [log in to unmask]
Subject: [TN] Flip-flop panels
Hi Technos,
the flip-flop nickname actually comes from the Technet, I heard it right
here some time (years) ago. What I mean is the panels made up by arrays
of alternating top-bottom patterns.
I know that the layer stackup has to be symmetrical, that the copper
weight has to be symmetrical, but what about the controlled impedance
boards? Let's say a 12 layer PCB, that calls for:
4.0 mil lines: 56 ohm trace impedance +/- 10% layers 2,4,5,8,9,11
6.5 mil lines: 50 ohm trace impedance +/- 10% layers 4,9,11
8.1 mil lines: 45 ohm trace impedance +/- 10% layers 4,8,9 8.0 mil
lines: 56 ohm trace impedance +/- 10% layers 1,12
Is this PCB a good candidate for flip-flopping?
And it is just now that I realized it has 12 layers? Any limitations
coming from layer count?
And even better, I have one other board with microvias and blind/burried
vias. Can this be flip-flopped?
Thank you,
Ioan
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