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March 2007

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Subject:
From:
"Tempea, Ioan" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Tempea, Ioan
Date:
Fri, 2 Mar 2007 14:15:33 -0500
Content-Type:
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text/plain (121 lines)
John,

Steve is right on the money. Best solution for JIT, one piece flow. When the mechanical-test-packing cell is almost out of boards, you just flip the boards half assembled, with no down time for changeover, and start supplying again.

Regards,

Ioan

-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Steve Gregory
Sent: Friday, March 02, 2007 2:09 PM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels


Hi John,

I've built panels that had flip-flopped boards before, (small narrow
double-sided SMT boards for a bar code reader pen), and it made things
so easy. One stencil, one SMT set-up, to do both sides of the panel on
one line.

After they come out of the reflow oven from the first side (and they've
cooled down of course), you just stick them right back in the screen
printer for the other side without so much as missing a beat...pretty
cool, eh?

-Steve Gregory-  

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of John Parsons
Sent: Friday, March 02, 2007 12:51 PM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels

Ioan,

Why would you want to design an array like this?

John Parsons

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tempea, Ioan
Sent: Friday, March 02, 2007 10:23 AM
To: [log in to unmask]
Subject: [TN] Flip-flop panels

Hi Technos,

the flip-flop nickname actually comes from the Technet, I heard it right
here some time (years) ago. What I mean is the panels made up by arrays
of alternating top-bottom patterns.

I know that the layer stackup has to be symmetrical, that the copper
weight has to be symmetrical, but what about the controlled impedance
boards? Let's say a 12 layer PCB, that calls for:
4.0 mil lines: 56 ohm trace impedance +/- 10% layers 2,4,5,8,9,11
6.5 mil lines: 50 ohm trace impedance +/- 10% layers 4,9,11
8.1 mil lines: 45 ohm trace impedance +/- 10% layers 4,8,9 8.0 mil
lines: 56 ohm trace impedance +/- 10% layers 1,12

Is this PCB a good candidate for flip-flopping?

And it is just now that I realized it has 12 layers? Any limitations
coming from layer count?

And even better, I have one other board with microvias and blind/burried
vias. Can this be flip-flopped?

Thank you,

Ioan

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