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March 2007

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Subject:
Re: Flip-flop panels
From:
John Parsons <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, John Parsons <[log in to unmask]>
Date:
Fri, 2 Mar 2007 10:51:18 -0800
Content-Type:
text/plain
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text/plain (62 lines) 
Ioan,

Why would you want to design an array like this?

John Parsons

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tempea, Ioan
Sent: Friday, March 02, 2007 10:23 AM
To: [log in to unmask]
Subject: [TN] Flip-flop panels

Hi Technos,

the flip-flop nickname actually comes from the Technet, I heard it right
here some time (years) ago. What I mean is the panels made up by arrays of
alternating top-bottom patterns.

I know that the layer stackup has to be symmetrical, that the copper weight
has to be symmetrical, but what about the controlled impedance boards? Let's
say a 12 layer PCB, that calls for:
4.0 mil lines: 56 ohm trace impedance +/- 10% layers 2,4,5,8,9,11
6.5 mil lines: 50 ohm trace impedance +/- 10% layers 4,9,11
8.1 mil lines: 45 ohm trace impedance +/- 10% layers 4,8,9
8.0 mil lines: 56 ohm trace impedance +/- 10% layers 1,12

Is this PCB a good candidate for flip-flopping?

And it is just now that I realized it has 12 layers? Any limitations coming
from layer count?

And even better, I have one other board with microvias and blind/burried
vias. Can this be flip-flopped?

Thank you,

Ioan

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