Victor,

we follow the rule, that no voids are allowed for MIL/SPACE products. Many 
standards say, that the bond material, either solder or adhesive, shall be 
100% visible all around the chip. Normally, if you apply that rule, there 
use to be no voids. Voids can have a negative impact on devices that produce 
a lot of heat, like processors, ASICS and power devices. However, you always 
get the question ' what is no voids like, can't even 10um voids be accepted? 
'. In that case, I have never seen a quantification. I think common sense 
should be used. If the voids are so large, that they are clearly seen with 
ultrasonic scans, you may draw the conclusion, that  those packages should 
not be classified as good ones.
Example:

http://xweb.nrl.navy.mil/glast/CALDesign/CDE/GLAST%20LAT%20CAL%20Dual%20PIN%20Photodiode%20Spec%20LAT-DS-00209-11a.pdf

Inge

----- Original Message ----- 
From: "Victor G. Hernandez" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, March 13, 2007 12:55 PM
Subject: [TN] BGA Die Attach Criteria


Fellow TechNetters:

   Where can I locate die attach requirements for a BGA.   I see some
die attach voiding at the corner of the die and appear wrinkle.

Victor,

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