Wayne,
1. There are 100us pulse packages for a second or fraction of a second on
all a0 - a17
2. There are pulses on all d0 - d7 to for a short moment.
3. All three devices goes to High on Done (if I wait 15 seconds before
switching on power again)
4. INIT shows a pulse train too before going to High.
The conclusion may be that the 4013s are all OK.
The reason for all this troubleshooting is, that the PC screen has a Status
display, that shows whether all functions work or not. E.g. encoders , CPU
alive, motor functions etc. The FPGAs are involved in this presentation.
The fact that there is no movement at all on the Status screen, may not be
because of dead FPGAs then, but may be caused by other devices that send
inhibit or shutdown signals to the FPGAs.
So, with your help, it seems as we can conclude, that the 4013s get
configured, and that the failure is to be searched for somewhere else. How
to find that/those failure sources, that's another story, which seems to be
offside my original question.
Thanks Wayne, we may continue offline ?
Inge
----- Original Message -----
From: "Wayne Thayer" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, March 12, 2007 1:56 PM
Subject: Re: [TN] FPGA (DSP)
> Inge-
>
> Haven't run across that particular problem, but it sounds like a
> potential issue for "Master" mode, wherein the FPGA generates CCLK. The
> way something like that is usually fixed is by having something like a
> reset controller hold the /PROGRAM input of the part active until you're
> certain the power supply is up.
>
> By monitoring INIT and DONE, you can tell if the part thinks its
> configuring properly. INIT should be low until the device begins
> reading in its configuration and then it should stay high. DONE should
> be low until the device is completely configured, and then go high.
> There are CRCs in the data stream configuring the part, so random inputs
> or an incorrect configuration will cause INIT to go low while the device
> is attempting to configure. This is what would most likely happen if
> there were a power supply rise time problem. If you convince yourself
> that the device thinks it properly configured, then you don't need to
> worry about supply rise time, master/slave mode, unprogrammed FLASH, or
> any other initialization issues. If the same configuration runs
> correctly on another similar device, then it's time to start looking at
> interconnects, bad parts, or other portions of the design.
>
> If you do get a logic expert in, hopefully it will be someone who can
> write configurations for the Xilinx and download them over the JTAG
> port. The top Xilinx experts can actually read the configuration which
> is stored in the device to confirm it is set up properly. This is
> something Xilinx toyed with supporting during the 4000 series parts, so
> some documentation hints at how to do it, but the support was dropped.
>
> Wayne
>
>>>> [log in to unmask] 3/12/2007 7:14 am >>>
> Wayne,
>
> Got another tip from a TechNet guy, happened to erase sender. I was
> told
> that some elder FPGAs from Xilinx do not configure properly if the
> power
> supply is too slow from zero to +5V. The FPGA want <4ms rise time,
> while
> many power supplies are >>4ms. If the supply is slow, you need a hold
> off until safe 5VDC. But don't you need a power supply monitor to tell
> the PROM to hold off? (Thought the PROM was intelligent in itself, and
> had it's own voltage monitoring.) He may be right, because, in fact,
> one
> of the FPGAs does not go 'high' on DONE pin.
>
> Many thanks
>
> Inge
>
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Inge
> Sent: den 11 mars 2007 23:12
> To: [log in to unmask]
> Subject: Re: [TN] FPGA (DSP)
>
> Wayne,
> CCLK pin = 0.2us pulses (bits?) for about 1 second when power is
> switched on, then CCLK is steady 'High'
> ad0-ad17 from flash to FPGA= no continous bitstream Done=High /
> Init=High (donow what state is normal) ?
> Inge
>
> ----- Original Message -----
> From: "Wayne Thayer" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Sunday, March 11, 2007 3:59 PM
> Subject: Re: [TN] FPGA (DSP)
>
>
>> Hi Inge!
>>
>> Send the board to a logic specialist!
>>
>> It sounds like the part isn't configuring. Debugging that usually
>> requires no more than an oscilloscope, except that it depends on
> whether
>> the board designer left access to the important pins. I don't have
> the
>> data sheet in front of me right now, but some of the key pins for
>> configuration include: Two "Mode" pins, which control how the
> device
>> configures (slave, where someone else provides the clock; master,
> where
>> the Xilinx provides the clock; serial data configuration mode; or
>> parallel configuration mode); CCLK, which stands for "configuration
>> clock"; INIT, which can hold off configuration; and DONE, which
> tells
>> you whether the device thinks it configured. Also, there is the
> serial
>> data line (or parallel data bus for the parallel configuration)
> which
>> carries the configuration from the flash to the part. The first
> thing
>> to do is to get an oscilloscope on CCLK. If none comes up when the
>> power is first applied, then probably INIT or the MODE pins are not
> in
>> the right state. If there is no movement on the DATA line(s) going
> from
>> the flash to the 4013, then maybe someone forgot to program the
> FLASH.
>> INIT is mostly an input which causes re-configuration, but if you
> review
>> the data sheet for the part, you will also see that INIT is also an
>> output indicator that something is wrong with the configuration bit
>> stream.
>>
>> As I said, as long as you can get to the signals, you can figure
> this
>> out. Even if its a BGA, the ones made at that time had lines
> running
> to
>> the edge of the part which were for "bussing" for gold plating the
>> wirebond pads.
>>
>> Good Luck,
>>
>> Wayne Thayer
>>
>>>>> [log in to unmask] >>>
>> Hi all,
>> TechNet member's knowhow got no limits, so I try this, despite not
> usual
>> PWB topic. Have some FPGAs for DSP that don't work at all. CLK A and
> B
>> are OK, checked with a scope on the inputs, all 5V Vcc's are OK,
> but
>> when I apply stimuli on the various inputs, I get no reaction on any
>> data outputs. Very primitive test method, I know, but I thought that
> at
>> least something would come out to show that the device isn't
> completly
>> dead. The flash memory is external, I've tried with both disabled
> and
>> enabled flash, nothing helps. I can't remove the FPGAs, so I have to
>> test them on the assembled board. I've tried various triggers too.
> An
>> advanced troubleshooting would include logic analysers, external
> pattern
>> generators and a special test adapter. That's for a logic specalist,
>> which I'm not. My question is this: Does anyone of you have a
> proposal
>> how to test, simple way, if the FPGAs are dead or alive? The FPGAs
> are
>> Xilinx 4013, made in numbers of 'millions', very popular some years
> ago.
>> A fresh board costs 30,000 USD, hoped to escape that cost.
>> Inge
>>
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