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February 2007

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Subject:
From:
"Kane, Amol (349)" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Kane, Amol (349)
Date:
Thu, 8 Feb 2007 07:03:13 -0500
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Thank you everybody for their feedback.

Amol


 -----Original Message-----
From: 	TechNet [mailto:[log in to unmask]]  On Behalf Of Hogg, Blair K.
Sent:	Monday, February 05, 2007 9:28 AM
To:	[log in to unmask]
Subject:	Re: [TN] Conformal Coating Masking Requirements

Amol,

We use an Asymtek coating machine which avoids the need for masking. For
keep out areas the machine is programmed to skip these, and we make sure
that as a minimum all soldered areas are coated so that the solder
masked area around a keep out may or may not be coated. If a .100
diameter test point is needed to be left uncoated, we may leave a .250
square area around the keep out uncoated as long as it doesn't leave any
soldered areas exposed. As an OEM, we can make realistic decisions
in-house on how to perform our coating process. CMs can't be as
flexible, as they need to make sure that the result is acceptable to the
customer.

We test before coating, so we don't have to mask or skip test points
during the process. 

Blair 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Kane, Amol (349)
Sent: Monday, February 05, 2007 9:07 AM
To: [log in to unmask]
Subject: [TN] Conformal Coating Masking Requirements

Dear all,

Since we are on the topic of conformal coating, I wanted to get a feel
for how conformal coating masking requirements are being requested by
the customer and being handled by the manufacturers. The customer
drawing usually states the type of CC to be used and the keep-out areas
for the coating (usually location Ids on the board). When one is masking
on the keep-out areas, what tolerances are being used around the
keep-out areas?.......IPC 610 D only states that there should be no CC
on keep-out areas, and therefore by logical deduction, also assumes that
all areas except the keep-out areas are to be covered by coating.

Obviously, there are practical limitations to this requirement. For
example, a test via is a keep-out area, but the trace running from the
via is not. Is everybody out there JUST masking the via, and then doing
manual touch up on the extra keep-out area if any, afterwards? If one
goes too close, the coating flows on the keep-out area, and if one
leaves some space, you are violating IPC specs! .,..........I am
thinking along the lines of asking customers to specify a tolerance for
the keep-out areas as some of them are very particular about this issue.


Requesting your thoughts, current best practices etc

Regards,
Amol


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