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February 2007

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Subject:
From:
Steve Gregory <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Steve Gregory <[log in to unmask]>
Date:
Tue, 27 Feb 2007 12:26:23 -0600
Content-Type:
text/plain
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text/plain (74 lines)
Hi Carl!

I've run across some via-in-pad designs that were a major pain. They
were supposed to be filled and cap plated, then planarized, but this is
what I got:

http://www.stevezeva.homestead.com/files/Raised_Vias.jpg

Fun stuff eh? That's when I took a board and did a very rough
cross-section with my trusty dremel tool just to see what was going on
and why the bumps were so big.

http://www.stevezeva.homestead.com/files/Rough_Cross_Section.jpg

http://www.stevezeva.homestead.com/files/Cross_Section.jpg

I was somewhat able to compensate with solder paste...I think it was the
first time in a L-O-O-O-N-G while I ordered a 10-mil thick stencil.

Just hope that you don't get boards back like these if you decide to go
that route.

-Steve Gregory-

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Carl VanWormer
Sent: Tuesday, February 27, 2007 10:58 AM
To: [log in to unmask]
Subject: [TN] Via in Pad question

I am looking for guidance on using vias in pads of surface mount
components.  The concept is great for high speed design, since it gives
the least inductance for mounting bypass caps.  It sounds easy, but I'm
sure there are some pitfalls and there may be some rules I will break.
Any guidance towards documents on this combination would be appreciated.
Also, any stories to scare me away from this approach will be fun to
hear.

Later,
Carl





Carl Van Wormer
Cipher Systems
1800 NW 169th Place, Suite B-100
Beaverton, OR  97006
Phone (503)-617-7447 extension 20    

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