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Subject:	Re: Via in Pad question
From:	"Upton, Shawn" <[log in to unmask]>
Reply To:	TechNet E-Mail Forum <[log in to unmask]>, Upton, Shawn
Date:	Tue, 27 Feb 2007 12:56:19 -0500
Content-Type:	text/plain
Parts/Attachments:	text/plain (52 lines)

I've avoid doing this, but then again, I've avoided microvias, sticking
instead of 15mil vias as a rule.  The problem is, at least on the larger
vias, is that when the part is soldered down (via whatever method), the
solder can wick into the hole, leaving the pad dry.  I'd think you could
also have a heat problem, if the the via goes to an internal plane with
no thermal reliefs then that pad could be cool during soldering.

But I don't have a lot experience in this area either.

Shawn Upton, KB1CKT
Test Engineer
Allegro MicroSystems, Inc
[log in to unmask]
603.626.2429/fax: 603.641.5336

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Carl VanWormer
Sent: Tuesday, February 27, 2007 11:58 AM
To: [log in to unmask]
Subject: [TN] Via in Pad question

I am looking for guidance on using vias in pads of surface mount
components.  The concept is great for high speed design, since it gives
the least inductance for mounting bypass caps.  It sounds easy, but I'm
sure there are some pitfalls and there may be some rules I will break.
Any guidance towards documents on this combination would be appreciated.
Also, any stories to scare me away from this approach will be fun to
hear.

Later,
Carl





Carl Van Wormer
Cipher Systems
1800 NW 169th Place, Suite B-100
Beaverton, OR  97006
Phone (503)-617-7447 extension 20    

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