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February 2007

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From:
Wayne Thayer <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Wayne Thayer <[log in to unmask]>
Date:
Sun, 25 Feb 2007 18:53:12 -0500
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We are placing test coupons on most of our orders.  One of these is for Tg--More than once I have spec'd high Tg material which has not produced high Tg assemblies.  The problem is usually that the circuit board fab uses high Tg core material, but uses the low Tg pre-preg!  Another test coupon is for IST (interconnect stress test).  This can be used to qualify the boards prior to a large assembly run because if the blame finger points to the board fab, they won't pay for the lost assembly parts and labor.

Wayne Thayer

>>> [log in to unmask]  >>>
Hi John,

You have already received some good advice from Joe, Kim and especially Werner, whom I have learned to pay particular attention.  I would like to add a few comments.

Copper quality is usually the primary influence in circuit board reliability but, with lead/free assembly, material is beginning to play a greater role.

I did not notice if you mentioned whether you were using tin/lead (230°C) or lead/free (260°C) assembly temperatures.  If you used tin/lead assembly you should find barrel cracks in the central zone of the plated through via (PTV).  Tin/lead assembly shifts failure, to some degree, away from the central zone  and up to corner of the PTV where you will find an increase in knee cracks.

When you are faced with one set of boards that are fine and an other set failing, and all process and board parameters appear to be similar, by microsection measurements, then the material must be considered.  In your case delamination may be playing role. It turns out that delamination de-stresses PTV and protects them from failing during thermal cycling.  I would look for evidence of delamination in the dielectric as a latent failure mode on any microsections processed.

Another useful bit of information about printed circuit board (PCB) material embraces hysteresis.  One definition of hysteresis is a failure to return to the original condition. In the case of circuit boards we sometimes find damaged circuits (barrel cracks) show no increased resistance at ambient (~22°C); they are self healing.  Other damaged circuits present an increased resistance at ambient.  The circuits that maintain an elevated resistance at ambient condition are exhibiting a resistance hysteresis.  

IPC (6012) has establishes that a 10% increase in resistance in a circuit is considered a failure.  We frequently find boards that are elevated 10% above of their normal resistance at 150°C, show no increase in their original resistance at ambient. This makes it particularly hard for trouble shooting via failures.  The changes are usually so subtle you need to make resistance measurements using a 4-wire ohmmeter.

To understand this phenomenon we need to understand dielectric material.  Normally the dielectric is elastic and, after a thermal cycle, returns to it's original shape at ambient. Barrel cracks are forced closed at ambient due to the dielectric's elastic properties, and resistance returns to the original measurement.  If, on the other hand, the dielectric has lost its elasticity, a typical response to multiple or higher temperature cycling, it will undergo plastic deformation and will not return to its original shape at ambient, resistance remains elevated. Barrel cracks in PTVs in a board where the dielectric is plastic will show evidence of hysteresis and circuit resistance will remain elevated at ambient.

A bed of nail continuity test is usually not capable of finding resistance increases that are in the order of 10%. Boards that exhibit hysteresis due to plastic deformation of the dielectric that keep barrel cracks open at ambient have a better chance of being found with ET.  Kim's finding increased amount of damage is probably due to accumulating damage and a slowly degrading dielectric that is losing its elasticity. 


Sincerely,

Paul Reid

Program Coordinator

PWB Interconnect Solutions Inc.
235 Stafford Rd., West, Unit 103
Nepean, Ontario
Canada, K2H 9C1

613 596 4244 ext. 229
[log in to unmask] <mailto:[log in to unmask]> 

---chNet [mailto:[log in to unmask]]On Behalf Of John Foster
Sent: Saturday, February 24, 2007 1:43 PM
To: [log in to unmask]
Subject: [TN] need help with cracking vias


I was wondering if I could get a opinion on some problems
we are having with vias. Built two different types of getek boards
10 layer .062. Both types have over 2000 10 mil vias. One set
of boards went through everything and are doing fine. The other
set went through the same fab shop and same assembly shop.

The second set of boards passed electrical test at the fab house but
after assembly and the start of useage the boards are developing 
opens like crazy in the 10 mil holes. I am going over on Monday to
get some cross sections of actual bad vias. I just wanted to
get some ideas of what to look for. If the barrels show cracks
can you tell anything by where the cracks are? If the plating
is too thin will it make the vias much more likely to crack during reflow.

I am just trying to really understand what happened so that it doesn't happen
again. But the vias just continue to open you fix one and the board works
for awhile and then another one opens up.

I am thinking that if there is adequate plating in the bad holes then the assembly
shop either ran the boards to hot or for too long and the z axis expansion killed
me. Is it possible that something in the plating process caused the vias to
be inadeqaute. Doesn't the plating have to have some ductility to it?


any input will really be appreciated

Thanks
John Foster

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