The photo's you provided clearly show bonding failures under conductors
and land areas.  The spacing metric in the IPC requires the delamination
does not encroach conductive patterns into more than 75% of the
available spacing.  This is to ensure the conductor areas have both
encapsulation and surface bond integrity - with the added requirement of
testing for propagation.

Buy new boards.  

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of pearl petras
Sent: Thursday, November 30, 2006 10:08 AM
To: [log in to unmask]
Subject: Re: [TN] More delam

Well, there have been several related discussions on this, but I really
would like to hear what people think about my original questions, if
possible.
  1. Are any of these fixable?
  2. Would you try, or would you just let them go, or would you scrap
them?
  3. Can someone interpret what IPC-A-600 means by:
  -The blister or delamination does not span more than 25% of the
distance between adjacent conductive patterns.
  (adj patterns on the same layer as the delam, or adj patterns on any
layer in the board or ...?)  For instance, dctest2.jpg spans the
conductive patterns on the top layer, but the delam is on an internal
layer (of course).
  Thank you.
  http://stevezeva.homestead.com/files/bigdelam1.JPG
http://stevezeva.homestead.com/files/dctest1.JPG
http://stevezeva.homestead.com/files/dctest2.JPG
http://stevezeva.homestead.com/files/mcx.JPG

----- Original Message -----
From: "pearl petras"
Sent: Monday, November 27, 2006 10:02 AM
Subject: [TN] More delam

> Arggghh,
> More delamination. Looks like poor quality PCB's - a simple quick test
> adjustment to a component seems to be causing a lot of boards to 'pop'
in
> the same area. As well, others are popping in the area of a
> hand-installed edge connector, when they start to solder the center
pin.
> Even just tinning the pad does it sometimes.
> What would you do with boards like this?
> Would you try to fix it? How?
> Would you scrap it? There are some very expensive IC's on this board.
> Do you think it may go deeper than one layer?
> It is a 10 layer PCB
> IPC-A-600 states:
> -The imperfection does not reduce the space between conductive
patterns
> below the minimum conductor spacing. (OK - minimum conductor spacing
for
> low voltage is ~0.1mm)
> -The blister or delamination does not span more than 25% of the
distance
> between adjacent conductive patterns. (What does this mean? adj
patterns
> on the same layer as the delam? or do you consider 3-D, if the
conductive
> patterns are on a different layer but the bubble spans underneath
them?)
> -There is no propagation as a result of thermal testing that
replicates
> the manufacturing process. (would you try more hand-soldering, or
would
> you try a reflow process, how would you mimic it?)
>
>
>
> Steve, could I trouble you to post another few pics?
>
> Thanks all.
>


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