TechNet Friends,

I was wondering if anyone could supply me with a comment regarding board
warpage and reliability...

Our old test and acceptance standard was developed around a maximum of 1000
microstrains.  Readings above this supposedly would result in sporadic
cracking of the larger sized ceramic chip capacitors or resistors.

Since part dimensions have become smaller, might I assume the 1000
microstrain limit could be safely extended (with testing for confirmation,
of course)?

The bow and twist specs set forth in IPC-A-610D state that after solder
conditions should not exceed 0.75% for surface mount applications.  Was
this spec set by the committee after some sort of reliability testing?  If
so, does anyone know if the study has been made available for reference?

Many thanks in advance,

Leland Woodall
Quality Coordinator

Keihin Carolina System Technology, Inc.

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