Steve,

My first thought would be too much paste on the exposed pad (tab/paddle etc) which lifts the part too high to allow the terminal
pads to form joints. Are there any unfilled via's on the exposed pad footprint?


Best Regards

David Greig
______________________________
GigaDyne Ltd
Buchan House
Carnegie Campus
Dunfermline KY11 8PL
United Kingdom
t: +44 (0)1383 624 975
www.gigadyne.co.uk
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
Sent: 31 August 2006 19:58
To: [log in to unmask]
Subject: [TN] LLP (Leadless Leadframe Package) headaches...

Good Afternoon my fellow esteemed TechNet-ologists,

We're building a little double sided SMT board that has a National Semi 6-pin LLP (Leadless Leadframe Package) device on it.
We call this little board a "Leaf" board because of it's shape:
http://stevezeva.homestead.com/files/LLP.jpg

The problem on this board is the LLP device. We've gotten quite a few boards back from test stating that the board failed test
and that U4 needed to be re-reflowed.

This is not the first time I've heard this prognosis from a test department to correct a problem with a board. Almost every time
I've looked into this issue, I've not seen a problem with the solder joint, or a problem with the reflow profile, or anything
else that you would naturally look at to try and explain why re-reflowing would correct the problem. Not to mention the fact
that the parts that are right next to the questionable device are fine with no problems whatsoever. Yet when you re-reflow the
part it will usually pass test the second time around.

I've had this happen with QFP's, SOIC's, PLCC's, and now this LLP.
Obviously it must have something to do with the solder joint, but what is it man?!?! I've scratched my head about this more than
a few times.

What does re-reflowing a perfectly good looking solder joint cause a board to pass test where it didn't pass before?

-Steve Gregory-

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