John:
Arcing in between layer will burn the material used and create a
carbon path. In this manner the cathode will short with the anode.
Regards,
Ramon
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of John Burke
Sent: Tuesday, September 26, 2006 4:57 PM
To: [log in to unmask]
Subject: Re: [TN] High-Voltage Board Spacings
Interesting observation Joyce,
I would imagine it is somewhat self limiting. A caf event takes places
as the anodic filament gows until it touches the cathode, and I have
typically seen this on boards with distributed 48v DC The events are not
always catastrophic as the CAF event generally "fuses" as it touches due
to the high current availability. So the CAF event is somewhat
progressive in nature, each event degrading the resistance of the
channel until finally it becomes a show stopper.
In a high voltage scenario though wouldn't it more take the form of
arcing, so in fact the anodic filament never reaches the cathode??
John
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Joyce Koo
Sent: Tuesday, September 26, 2006 12:40 PM
To: [log in to unmask]
Subject: Re: [TN] High-Voltage Board Spacings
just curious, does anyone see high voltage CAF (I mean >700-1000V)?
thanks.
jk
abcd
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Hfjord
Sent: Tuesday, September 26, 2006 3:27 PM
To: [log in to unmask]
Subject: Re: [TN] High-Voltage Board Spacings
We are not allowed to have more than 500 Volts between surface traces
and layers below . Over 500 Volts, FR-4 is not used because of the
humidity risks, also high altitude phenomenons, like corona effects. For
1500 Volts we would typically use PTFE 1500 Volts means a high
activation and the board is therefore much more susceptible to migration
and other high voltage driven disasters. The dielectric withstanding is
expressed in kV/mm, e.g. 40 kV/mm, and it makes people think kV rather
than Volts. I represent HiRel and Mil manufacturing, I can imagine that
the home electric equipment industry, and other commercials, have a less
stringent desing rule here.
Inge
----- Original Message -----
From: "Wayne Thayer" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, September 25, 2006 11:41 PM
Subject: Re: [TN] High-Voltage Board Spacings
> Your failure mode of deepest concern is most likely CAF (Conductive
> Anodic Filament). The most common spot for this problem is via to
> trace, and the seed is disturbances in the via side wall. CAF can
> also grow along glass filaments within pre-preg from layer to layer.
> Failure potentials are at less than 10% of the 750V/mil. Laminates
> are available with very high CAF resistance if you need to push
> things. I believe there are some BT based materials that are
> virtually immune, but 1500V is a lot of potential!
>
> Wayne Thayer
>
>>>> [log in to unmask] 9/25/2006 5:06 pm >>>
> Should I be using IPC Table 6.1 for conductor spacing for high voltage
> in the z-axis of the pcb?
> Or should I be using the approximately 750V/mil spec from the laminate
> supplier and derate that number?
> Board has +/- 1200V.
>
> Thank you.
>
> Kaye Clayo
> Sr. P. C. Layout Designer
> Keithley Instruments, Inc.
> 440-498-2862
>
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