Shannon,
YES, you violate the spec both in letter and intention.
Dewey is right and your PM needs to listen to the experts (that would
include you).
It is you task to make it right as it is the PM's task to get it
released.
Tell your PM to sit down, take a break and wait until you can fix the
artwork to not violate common design rules.
Good Luck,
FNK
Frank N Kimmey CID+
Principal PCB Designer
PCB Programs
Powerwave Technologies Inc
Office 916-941-3159
Fax 916-941-3195
Mobile 916-670-0645
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Abel, Shannon K.
Sent: Thursday, September 21, 2006 8:13 AM
To: [log in to unmask]
Subject: Re: [TN] Mechanical Hardware Clearance...
It is relavent when my PM is asking. While I know its not best
practice, I need to find what the correct answer is.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Whittaker, Dewey
(EHCOE)
Sent: Thursday, September 21, 2006 11:01 AM
To: [log in to unmask]
Subject: Re: [TN] Mechanical Hardware Clearance...
IMHO
It is irrelevant whether you violated any guideline or not. Do not ever
mount any conductive entity over a trace which then relies solely on the
SM for electrical protection.
Dewey
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Abel, Shannon K.
Sent: Thursday, September 21, 2006 7:44 AM
To: [log in to unmask]
Subject: [TN] Mechanical Hardware Clearance...
I have a board with a 15VDC trace on the surface layer that runs under a
flat washer.
The trace is covered by SM, which provides 500vdc isolation per .001 mil
of SM coating.
2221 states that any electrical conduction trace per sec 6.3 lists a
minimum clearance of .00512 to any other conductive surface (.ie
mechanical hardware)
Do I violate the spec.
Any help would be greatly appreciated.
Shannon Abel
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