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September 2006

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Subject:
From:
"Whittaker, Dewey (EHCOE)" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Whittaker, Dewey (EHCOE)
Date:
Thu, 21 Sep 2006 08:01:18 -0700
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text/plain
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IMHO
It is irrelevant whether you violated any guideline or not. Do not ever
mount any conductive entity over a trace which then relies solely on the
SM for electrical protection.
Dewey 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Abel, Shannon K.
Sent: Thursday, September 21, 2006 7:44 AM
To: [log in to unmask]
Subject: [TN] Mechanical Hardware Clearance...

I have a board with a 15VDC trace on the surface layer that runs under a
flat washer.  

The trace is covered by SM, which provides 500vdc isolation per .001 mil
of SM coating. 

2221 states that any electrical conduction trace per sec 6.3 lists a
minimum clearance of .00512 to any other conductive surface (.ie
mechanical hardware)

Do I violate the spec.

Any help would be greatly appreciated.

Shannon Abel





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