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September 2006

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Subject:
From:
John Burke <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, John Burke <[log in to unmask]>
Date:
Mon, 18 Sep 2006 18:02:37 -0700
Content-Type:
text/plain
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text/plain (120 lines)
I and a colleague actually designed a test panel which replicated this
condition. It is generally a function of the hole size (smaller is worst)
and the aspect ratio (higher is worst). Blocking with resist prevents fluid
change over, but when they are all on the same net this is unlikely as a
cause.

The test panel we created took via holes of 8 mil to 22 mil in a 110 mil
thick multi layer panel. Each hole size was replicated into a BGA design.
Some holes were signal, some power, and some ground replicating an actual
design scenario.

Basically the panel when put down a board line gives a visual indication of
where the technology fails in terms of aspect ratio, stripping, Bernoulli's
laws etc. So an immediate and visual indicator of hole size for aspect ratio
can be assessed for the line, and the line tweaked accordingly.

The panel was created to test the capability of a board line to eliminate
skip plating, and was a project by myself and James Townsend at Extreme
Networks.

I believe Extreme own the copyright on this board which James (JT) and I
named FDAT (Fluid dynamics assessment tool) but which is also affectionately
known as the Bernoulli bus.

If anyone wants to try it, I will ping JT to see if the artwork could be
released as this work is now over 3 years old.

John

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Franklin D Asbell
Sent: Monday, September 18, 2006 5:14 PM
To: [log in to unmask]
Subject: Re: [TN] ENIG

I've witnessed sporadic poor covered pads but never even considered
verifying their connection via traces to the varied pads.

Typical cause in the majority I observed were poor tin strip/poor predip
(75% of observed) and poor resist develop (15% of observed) with the
remaining undetermined.

Of the observations made above, these were in instances where we confirmed
bath operating optimally.

Is there enough (electrical) activity occurring in these baths where a short
or other board condition would result in robbing plating from those type
areas???

Franklin

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Dennis Fritz
Sent: Monday, September 18, 2006 7:03 PM
To: [log in to unmask]
Subject: Re: [TN] ENIG

In a message dated 9/18/2006 7:50:57 P.M. Eastern Daylight Time,
[log in to unmask] writes:

There is  one thing I did leave out. The pads that aren't taking ENIG all
happen to be  in the same net. Has anyone encountered this?


To me, this says that there is some "electrical" cause, stronger than the
catalyst that initiates the electroless nickel plating.  Remember, the
catalyst in the ENIG process is a tightrope between getting plating
everywhere (extraneous plating) and not covering some pads (skip plating).
Here you  have skip plating

 If the same net skips board-to-board, likely it is a design issue  where
something is grounded out unintentionally and plating is getting defeated
in one spot. It could be that some via is tented consistantly holding a
poisoning fluid - tin stripper for instance.  If different nets skip on the
panel, then I suspect a more random error - incomplete tin strip, etc. I
guess  it could
be marginally weak catalyst.   I would expect developer residues  to be
random
pads - not all in a single net. Something "electrical" is going on  here.

Denny Fritz
MacDermid

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