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September 2006

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Subject:
From:
"Whittaker, Dewey (EHCOE)" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Whittaker, Dewey (EHCOE)
Date:
Mon, 18 Sep 2006 14:37:07 -0700
Content-Type:
text/plain
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text/plain (117 lines)
It leads to separation anxiety. 

It depends.

There are specific design and end use environment requirements, which
could have a potential impact on whether the capacity existed to allow
some delamination. A few rules of thumb( if this was for lead-free, it
would be green thumb):

*         Do not accept if it decreases dielectric spacing by more than
50%

*         Do not accept if it propagates

*         Do not accept for high voltage applications

*         Do not accept if humidity is a concern

*         Do not accept if minimum dielectric spacing is 0.006 inches or
less

*         Do not accept if it fails CAF testing

 

Dewey

 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Pasquito, Helena
Sent: Tuesday, September 12, 2006 9:45 AM
To: [log in to unmask]
Subject: [TN] Delamination

 

Hi TechNetters,

 

Let me ask a question; I know delamination is bad, but why?  What is the

failure mode to the board when a board delaminates and would there ever

be an instance that a board that delaminates is still OK to use?  This

is a Class 3 application.  Yes, I know what the IPC standards say but

not real sure about the board process.  Yes, I "googled" and there is a

lot of stuff out there.  Maybe someone can recommend some reading

material (hopefully short and sweet and to the point).

 

Thanks!

Helena  

 

Helena Pasquito

Manufacturing Skills Instructor

M/A-COM, Tyco Electronics

1011 Pawtucket Blvd., M/S 107

Lowell, MA 01853

978-442-5024

[log in to unmask]

 

 

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