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August 2006

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Subject:
From:
"Gregg A. Owens" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Gregg A. Owens
Date:
Wed, 9 Aug 2006 20:09:53 -0700
Content-Type:
text/plain
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text/plain (88 lines)
J-STD-001D 7.6.4 requires an end joint height of 25% fillet height up
the end of the chip:

G + 25% H or G + 0.5mm whichever is less (with G = solder fillet
thickness and H = termination height).

J-STD-001D 4.14 All solder connections shall (defect Class 1, 2, 3)
indicate evidence of wetting and adherence where the solder blends to
the soldered surface.

IPC-A-610D Section 5 (page 5-1) basically quotes the same verbiage
J-STD-001D 4.14 regarding wetting.

Lines of demarcation between the solder and the soldered surface are not
necessarily evidence of non-wetting or dewetting of the solder
connection. A visual examination judging the proper creation of an
internal intermetallic is a difficult task to say the least.

The IPC-HDBK-610 6.1.0.2. Wetting and Solderability [last two
paragraphs]
"When the solder bonds or "wets" to metals a metallurgical reaction
takes place between the solder and the base metal. This reaction creates
a new metal alloy that is defined as the intermetallic. This
intermetallic layers holds the solder connection together.

In some cases solder connections there is a line of demarcation or
transition zone where the solder blends with the solder coating, plating
or other surface material. The line of demarcation is not an indication
of a defect. If the contact angle a the line is acceptable the solder
connection is considered acceptable."

So you very well may have acceptable solder connections on your hands. I
hope that these excerpts shed some light to your question.

Gregg A. Owens, MIT
Manufacturing Technology Training Center, Inc.
Mira Loma, CA 91752 USA


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Gervascio, Thomas
Sent: Monday, August 07, 2006 12:40 PM
To: [log in to unmask]
Subject: [TN] Chip component solderability requirements

I have a question about the solderabilty requirements on chip resistor
and capacitors per J-STD-001D. I have solder wetting up to the top of
chip components where in come cases there is a distinct line of
demarkation. In other cases the solder wets over the end termination of
the part and has a smooth wetting angle. Is a visible line of
demarkation rejectable per J-STD-001 soldering requirements (para 4.14).
The requirment is for a 50 percent solder fillet height and although a
smooth wetting angle is perferred - is a line of demarkation (non
wetting vs dewetting) a cause for rejection? I am using 63/37 eutectic
solder so the alloy is not exotic.

Thanks much
Tom Gervascio
Senior Process Engineer
Sypris Electronics

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