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August 2006

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TechNet E-Mail Forum <[log in to unmask]>, Hfjord <[log in to unmask]>
Date:
Mon, 7 Aug 2006 23:49:18 +0200
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Tom,
standards are nice to have, but one needs to have own opínions about what is
good and bad. What you describe calls for extra attention, would suggest a
wetting balance test and also an investigation of the soldered caps by means
of cross section and SEM/EDS. The 'demarkation' line can be coarse Lead
crystals or crystals of intermetallic nature, often with a greyish touch,
and with little negative impact. But to be sure that it ain't debris from a
bad wetting or dewetting, I'd look a little extra as like I said earlier.
Ingemar Hernefjord
Ericsson Microwave Systems


----- Original Message -----
From: "Gervascio, Thomas" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, August 07, 2006 9:39 PM
Subject: [TN] Chip component solderability requirements


I have a question about the solderabilty requirements on chip resistor
and capacitors per J-STD-001D. I have solder wetting up to the top of
chip components where in come cases there is a distinct line of
demarkation. In other cases the solder wets over the end termination of
the part and has a smooth wetting angle. Is a visible line of
demarkation rejectable per J-STD-001 soldering requirements (para 4.14).
The requirment is for a 50 percent solder fillet height and although a
smooth wetting angle is perferred - is a line of demarkation (non
wetting vs dewetting) a cause for rejection? I am using 63/37 eutectic
solder so the alloy is not exotic.

Thanks much
Tom Gervascio
Senior Process Engineer
Sypris Electronics

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