Pete,

How many coupons failed?  How many were sample? How many solder floats
and at what temperature?

Let discuss the laminate voids a little bit.  The edges of the samples
appear to be clean cut with little deformation of the material.
Assuming the edges were not ground, the sample removal process does not
appear to be the culprit.  Also the shape of the voids (rounded
appearance versus a wedge appearance caused sample removal) suggests the
voids are not due to sample removal.

The voids are not on the coupon with circuitry to the edge.  I am going
to assume this is the typical response for all the coupons.  Since
multiple coupons with thermal stress and circuitry to edge of the coupon
did not have voids, my first conclusion is this may not be a thermal
related defect.

I would investigate the location of the coupons on the panel and the
border file.  The coupons may be located in a low pressure ridge.  The
voids naturally move to this location during lamination and there is
insufficient vacuum draw or a poor border pattern that prevents the
escape of the air.  If this is the case, this is a flaw of the coupon
and not the product.

If the border file is not the issue, I would go back and investigate the
thermal stress again.  There is a series of additional investigations
that would be required for the thermal stress as well as documenting the
voids apparent using darkfield or DIC filtration.

I agree with Susan that I would microsection images adjacent to the
coupon.  Not to verify the images are good but also to see whether of
pressure ridges in the panel layout.

My approach Pete is the lab has reported an anomaly and has fulfilled
their role.  The board shop should supply data for their
investigation/conclusions and not let them IMO you to death.

Randy Reed
Merix Corporation
-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Menuez,
Pete (IE) @ CIN
Sent: Friday, July 21, 2006 8:19 AM
To: [log in to unmask]
Subject: [IPC-600-6012] Inspection area of Coupons

I've attached a picture of the coupon that brought up my question
yesterday.

The reason for my question and request for clear definition of the
evaluation area is that the user (me) can get put in the middle of an
argument and may not (probably doesn't) have the expertise to make an
educated opinion.  On one side you have the board fabricator saying that
it's good - not part of the coupon design etc. and the lab is saying its
on the coupon therefore its is rejected.

Bob Naves pointed out that a lab rejection is not the final say.  That's
an absolutely correct statement. But how does the end user (again, me)
make the decision whether the lab is correct or the fabricator is
correct?  Again, its a he-said-she-said argument.  I have been through
those arguments and they aren't pretty. These particular boards are 1
ups on a 18 x 26 panel and run north of $10,000 each.  This would be a
very bloody contest indeed.

What I'm suggesting is that we define the evaluation area for the
coupon. We do this for the thermal zones, why not do it for the entire
evaluation zone.

If there is concern that there are issues that might be missed (like
these laminate voids) that should be addressed then terminology that
says if non-conformances are found outside the evaluation zone a root
cause evaluation must be made by the fabricator. 





Pete Menuez
Supplier Quality Engineer
L-3 Communications Cincinnati Electronics
7500 Innovation Way
Mason, Ohio 45040
[log in to unmask]

513-573-6401 Voice
513-573-6767 Fax

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