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June 2006

DesignerCouncil@IPC.ORG

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Subject:
From:
Chris Ball <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Thu, 8 Jun 2006 10:32:27 -0400
Content-Type:
text/plain
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text/plain (126 lines)
Hiya Bill-

Here are notes pulled from a random assembly (units are MM):

THIS ASSEMBLY CONTAINS ESD SENSITIVE COMPONENTS. HANDLING TO BE IN
COMPLIANCE WITH CONTROL PLAN PER ANSI/ESD-S20.20-1999.
<we also place an ESD WARNING symbol on the drawing>

SUBSTANCE USE RESTRICTION PER VMAT-10052.
<this is a reference to an internal document which references a GM
substance restriction document (nothing to do with Rohsweeee)>

MATERIALS USED ON THIS ASSEMBLY TO BE PER ITEM 4.
<Item 4 being a ref. entry on the BOM to a document that specs a compatible
group of solders, fluxes, adhesive, conf.coat, etc.>

FINISHED ASSEMBLY MUST BE IN COMPLIANCE WITH IPC/EIA J-STD-001D, CLASS 3,
AND IPC-A-610D, CLASS 3.
<self explanatory, I hope>

ADDITIONAL CLEANLINESS REQUIREMENTS PER ITEM 5.
<Item 5 being a ref. entry on the BOM to a document that specs our req. for
both bareboard and assy cleanliness. Spec's levels and test methods;
tighter than stock IPC...>

AFTER SOLDERING COMPONENTS TO BOARD, APPLY CONFORMAL COAT TO TOP SIDE OF
BOARD AS SHOWN IN VIEW A. MATING SURFACES OF J1-J12 AND T1-T3 SHALL BE FREE
OF COATING PRIOR TO SOLDERING PCB ASSEMBLY INTO COVER. COAT ENTIRE BOTTOM
SIDE PER VIEW A AFTER SOLDERING PCB ASSEMBLY INTO COVER.
<this note varies for each assembly and works in conjunction with a view on
the drawing>

CONFORMAL COAT THICKNESS 0.025-0.20.
<varies based on type of coat used>

IN-CIRCUIT AND END OF LINE TEST PER ITEM 8.
<refs a spec>

ANNUAL PV TESTING PER ITEM 6.
<refs a spec>

BOARD EDGE IRREGULARITIES +/-0.25 ALLOWED AT ARRAY ATTACHMENT POINTS.
<varies depending no singulation method and packaging requirements>

Most of our boards also have a note referencing label placement/ink
permitted/laser etch proc./etc., and content of same. This board happened
to get all that on the next level assy. For some groups within the company,
we also add KPC-like symbols to some of the notes, which are keyed to an
niternal spec. As said earlier, ASSY notes are more indiviualized than our
other drawings, but you get the idea....

And though they are more or less 'standard', they are constantly evolving.
These are not representative of our entire organization, just some of the
US divisions.

Hope it's useful to you.

Best Regards,
-Chris





                       "Brooks,Bill"
                       <[log in to unmask]>                To:   [log in to unmask]
                       Sent by: DesignerCouncil          cc:
                       <[log in to unmask]>         Subject:    Re: [DC] Assembly notes?

                       06/02/2006 02:30 PM
                       Please respond to
                       "(Designers Council
                       Forum)"; Please respond to
                       "Brooks,Bill"







Nobody has standard assembly notes they can send me?


Bill Brooks
PCB Design Engineer, C.I.D.+
Tel: (760)597-1500 Fax: (760)597-1510
Datron World Communications, Inc.
Vista, California

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