Silicon Valley Chapter of the IPC Designers Council
Next Meeting is Tuesday, July 11 (11:30AM to 1:30PM)
The Beverly Heritage Hotel
(Santa Clara Room)
1820 Barber Lane
Milpitas, CA 95035
408-943-9080
http://www.beverlyheritage.com/
Sponsored by Zuken
http://www.zuken.com
Lunch will be a deli buffet
RSVP to [log in to unmask]
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Speaker: Gil White
Technical Marketing Manager
DDI - Anaheim, California
During the past 28 years, I have worked in the area of Electronic Interconnect, including Design, Fabrication, and Materials for electronic substrate. This includes MCM, BGA, and Flip Chip interposers & substrate, as well as Rigid, Flex, and Rigid-Flex PCBs. Education includes Electrical Engineering (BSEE) and a MBA with emphasis on Technology Management. Additionally, I have provided Technical Seminars in 14 countries within North America, Asia, Europe, and the UK.
Primary Topic:
• Embedded Capacitance
�� Definition - Materials & attributes
�� Design Guidelines & Constructions
• Embedded Resistance
�� Definition - Materials & attributes
�� Design Guidelines & Constructions
Secondary Topic (If time available)
• BGA Design Guidelines IPC Class 2 & 3
�� Hole-to-copper – Standard & Advanced
�� Drill diameter-to-pad diameter requirements
�� Drill to Pad to Aspect ratio requirements
�� Tracks per Channel & Trace & Space
�� Anti-Pad for plane clearance
�� 1.27 mm, 1 mm, 0.8 mm, 0.65 mm, 0.5 mm, & 0.4 mm
�� BGA off-Set Microvias
Please RSVP by July 7
Send to [log in to unmask]
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Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
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