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June 2006

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Sender:	DesignerCouncil <[log in to unmask]>
X-To:	Designers Council Forum <[log in to unmask]>, Silicon Valley Chapter - IPC <[log in to unmask]>
Date:	Tue, 27 Jun 2006 16:34:16 -0700
Reply-To:	"(Designers Council Forum)" <[log in to unmask]>, "Meadows, Peggy A" <[log in to unmask]>
Subject:	Re: Meeting Announcement: Silicon Valley Chapter >> July 11 (Hosted by Zuken)
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Content-Transfer-Encoding:	quoted-printable
Content-Type:	text/plain; charset="US-ASCII"
From:	"Meadows, Peggy A" <[log in to unmask]>
Parts/Attachments:	text/plain (101 lines)

RSVP to whom?

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
Silicon Valley Chapter - IPC
Sent: Tuesday, June 27, 2006 8:10 AM
To: [log in to unmask]
Subject: [DC] Meeting Announcement: Silicon Valley Chapter >> July 11
(Hosted by Zuken)

Silicon Valley Chapter of the IPC Designers Council

  Next Meeting is Tuesday, July 11  (11:30AM to 1:30PM)
    The Beverly Heritage Hotel
  (Santa Clara Room)

    1820 Barber Lane
Milpitas, CA 95035

    408-943-9080

    http://www.beverlyheritage.com/


  Sponsored by Zuken
  http://www.zuken.com
  Lunch will be a deli buffet
  ~  ~  ~  ~  ~  ~  ~  ~  ~  ~

  Speaker:  Gil White
  Technical Marketing Manager
  DDI  -  Anaheim, California

  During the past 28 years, I have worked in the area of Electronic
Interconnect, including Design, Fabrication, and Materials for
electronic substrate.  This includes MCM, BGA, and Flip Chip interposers
& substrate, as well as Rigid, Flex, and Rigid-Flex PCBs.  Education
includes Electrical Engineering  (BSEE) and a MBA with emphasis on
Technology Management.   Additionally, I have provided Technical
Seminars in 14 countries within North America, Asia, Europe, and the UK.

  Primary Topic:
  * Embedded Capacitance
  &#56256;&#56510; Definition - Materials & attributes
  &#56256;&#56510; Design Guidelines & Constructions
  * Embedded Resistance
  &#56256;&#56510; Definition - Materials & attributes
  &#56256;&#56510; Design Guidelines & Constructions

  Secondary Topic (If time available)
  * BGA Design Guidelines IPC Class 2 & 3
  &#56256;&#56510; Hole-to-copper - Standard & Advanced
  &#56256;&#56510; Drill diameter-to-pad diameter requirements
  &#56256;&#56510; Drill to Pad to Aspect ratio requirements
  &#56256;&#56510; Tracks per Channel & Trace & Space
  &#56256;&#56510; Anti-Pad for plane clearance
  &#56256;&#56510; 1.27 mm, 1 mm, 0.8 mm, 0.65 mm, 0.5 mm, & 0.4 mm
  &#56256;&#56510; BGA off-Set Microvias



  Please RSVP by July 7


  ~  ~  ~  ~  ~









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the BODY (NOT the subject field): SIGNOFF DesignerCouncil.
To temporarily stop/(restart) delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL/(MAIL)
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
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