Hi,
That's why we tell all our clients now to adjust their board blueprint MFG
NOTES with the following additional statements:

1. That the finished multilayer must withstand  (A)The LF assembly process
description including   a. Peak Temp   b. Time at Peak Temp    c Total
time above 250C on heating and cooling    d. Number of Cycles of  a.+b.+c.
    and   (B) If repair and rework is going to be performed and what those
Time & Temp will be.

2. That the finished multilayer must withstand 3 cycles of a 288C-10 sec.
solder-dip without delamination or hole cracking, measures and checked in
 (a) Ground-plane area    AND   (b) In the BGA area       before the board
is shipped.


Happy Holden
Asian Pacific Materials



"Stadem, Richard D." <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
05/26/2006 11:56 AM
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
"Stadem, Richard D." <[log in to unmask]>


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Subject
Re: [TN] Rohs Weeeeeee board material






That is the purpose of a thorough process/procedures audit done
periodically to ensure the material received is going to be good.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Tempea, Ioan
Sent: Friday, May 26, 2006 10:50 AM
To: [log in to unmask]
Subject: Re: [TN] Rohs Weeeeeee board material

Hi,

I guess we have a good idea now of the difficulties in specifying and
manufacturing lead-free capable PCBs. The next question that comes to my
mind is how are we going to assess if the PCBs that are well speced are
what we expect?

I mean, the spec can be OK, whether perfect IPC-4010 slash sheets are
developed, or STII is implanted. But the manufacturer might still use
expired prepregs, they can have lamination problems, and so on.

What tests shall a contract manufacturer or OEM with no in-house testing
capability impose, in order to have the confidence that they receive
what they specified?

Thanks,

Ioan

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