Usually, resistance is monitored continuously during these tests and the
important information is the number of cycles before failure. Was this
an Interconnect Stress Test arrangement, where the vias are heated by
passing a current through them?  I'm guessing not, since it was a daisy
chain and they all failed, whereas in the IST it would stop on or before
the first failure.

What was the temperature range for the thermal cycle test?  In order
for the boards to pass despite barrel cracks/breaks you would have to
make the case that the temperature range used was way too high for your
application.  So either the boards are bad or the test was useless.

Wayne Thayer

>>> [log in to unmask] 5/23/2006 2:52:57 am >>>
Hello Technetters,

  I need your help on the following thermal cycle test problem.

  Recently we asked our PCB suppliers to do 1000 cycle thermal cycle
test for 6L, daisy chain boards with plated through holes filled with
epoxy ink and cap plated on the top of the holes( or via-in-pad design).
 The resistance change before and after thermal cycle test is less than
5%, however the holes have complete barrel crack.  Have you seen this
kind of problem before?  Can I approve the supplier's test result?

  Here are some more information about the test for your reference.
  1) board thickness: 1mm (40mils)
  2) hole size: 20mils, 18mils, 15mils, 10mils.  All have complet
barrel crack except the holes of 10mils .

  Thanks for your help in advance!
  Chris


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