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April 2006

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Subject:
Re: Reliability of leadless packages on thick boards
From:
Werner Engelmaier <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Fri, 28 Apr 2006 14:39:59 EDT
Content-Type:
text/plain
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text/plain (43 lines) 
Hi "WTHAYER,"
Yes, using low-CTE PCBs can be a solution to SJ reliability problems for 
large ceramic components, particulalrly when done in combonation with large solder 
joint heights [high-melt solder balls, solder columns] or conpliant leads. 
But as you point out, you may be trading for other issues.

Werner

In a message dated 4/28/06 14:26:20, [log in to unmask] writes:
> If you HAVE TO use parts like that, try a low CTE PCB material, such as 
> Arlon 85NT.  This is nice stuff, with a listed CTE under 10ppm/C.  It goes up a 
> bit with high copper loading.  Very stable, Tg over 200C, but sucks up 
> moisture and is hell to board route without the edge fuzzing due to the aramid 
> fibers.
> 
> >>> [log in to unmask] 4/28/2006 1:47:58 pm >>>
> Hi Ioan,
> Castellated ceramic leadless chip carriers were a bad idea when the were
> developed in the '80s, and nothing has changed*oops, I forgot about that 
> SAC-stuff
> making things worse.
> The problem is not the 'castellations' per se, but the fact that they will
> not allow the CC to swim up. Thus, the solder joint thickness is at a 
> minimum,
> producing the worst-possible SJ reliability geometry--if you shim up the CC 
> to
> increase SJ height, you can get about the same as what you get with BGAs 
> with
> the same ball dimension.
> Putting large ceramic components on FR-4, castellated or not, is not a good
> idea.

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