Hiya Bill-
Our situation involves TO-263's (D2PAK). We're using 0.5MM holes on 1MM
centers, 100 per tab 1.6MM thk PCB (.062). 4 lyr board with some copper
mass on each layer, but no huge connected plane to carry away the heat.
Board is mounted to a housing/heatsink which is on chassis GND. Most of the
thermal via areas are not GND. The mechanical design is such that when
board is screwed down, there's some space between heat exchange area and
PCB. Thermal joint compound is used. Very carefully, I presume. Apparently,
the cost of sealpad vs. TJC is significant.
Thermally we're OK. The tab solder joints are robust, though some solder
does travel to bottom of board through the vias (which are open in the mask
on both sides). The concern is that irregular solder deposits on the bottom
could be large enough to short to heatsink.
The board finish is HASL. When we tent the bottom, the air knife leveling
on the top forces solder through the vias and creates a potentially worse
condition than what we see by leaving them open.
Still under development and fallback is to use sealpad.
BR,
-Chris
"Brooks,Bill"
<[log in to unmask]> To: [log in to unmask]
Sent by: TechNet cc:
<[log in to unmask]> Subject: Re: [TN] 56 pin LFCSP footprint
12/05/2005 12:07 PM
Please respond to TechNet
E-Mail Forum; Please
respond to "Brooks,Bill"
Hi Chris,
I downloaded the IPC-7351 viewer and looked at what they had. It was very
similar to what I ended up designing so that's nice confirmation if nothing
else.
I have still not determined how many thermal vias I will need. That will be
based upon the thermal load on the chip and the need to conduct heat out of
it to keep it within its operating parameters. Right now I don't have that
number.
Advice from others who have worked with these successfully in the past
indicated the best choice for handling the design of the vias was to keep
them small in diameter so they would not suck the solder away from the
belly
pad, and connect them to the far side plane to get better thermal transfer
to the air rather than trapping the heat inside the board on an internal
plane.
The app notes from Analog Devices talk some about the options and I didn't
like the idea of leaving soldermask under the 'belly pad' over the plated
through holes but leaving the surrounding pad open for soldering... it just
seemed a potential place for problems to develop. It is recommended that
via
diameter of 0.3 (12 mils) to 0.33mm is used set a pitch between 1.0 and
1.2mm or about 40 mil centers.
What size vias are you using? The wicking of the solder was also a concern
I
had with doing this footprint. Some suggested it would be more of a problem
with thinner boards than it would be with thicker boards.
I will go with the recommended pads and vias on this .062 thick board and
we
will see out it turns out on the proto. The concern I have now is the
soldering profile and I will discuss that with out Manufacturing Engineer
sometime today. I'd be very interested in hearing the particulars of your
situation there.
Best regards,
Bill Brooks - KG6VVP
PCB Design Engineer, C.I.D.+, C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
Datron World Communications, Inc.
_______________________________________
San Diego Chapter of the IPC Designers Council
Communications Officer, Web Manager
http://dcchapters.ipc.org/SanDiego/
http://pcbwizards.com
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, December 05, 2005 6:34 AM
To: TechNet E-Mail Forum; Brooks,Bill
Subject: Re: [TN] 56 pin LFCSP footprint
Hi Bill-
I saw that in some of the earlier replies, you had been referred to the
footprint available in IPC-7351. Is there a problem with using that config
that we should know about?
I'd like to hear about how you decide to handle the vias in the thermal
pad. Having issues with another pak type at present. In our case, the parts
solder just fine but the wicking through the holes causes a flatness
problem when mounting to a heatsink on the opposite side. Potential for
poking through the sealpad and we need to be electrically isolated. Tenting
the bottom side (LPI) was not the answer....
All the Best,
-Chris
"Brooks,Bill"
<[log in to unmask]> To:
[log in to unmask]
Sent by: TechNet cc:
<[log in to unmask]> Subject: Re:
[TN] 56 pin LFCSP footprint
12/02/2005 11:58 AM
Please respond to TechNet
E-Mail Forum; Please
respond to "Brooks,Bill"
Thanks...
I contacted AD and talked with a technical support representative... He's
looking into a footprint recommendation from their development team... He
also sent me an application note on the part. It seems it has a large
thermal 'belly pad', for lack of a better name, that gets soldered to the
board in the center of the part. They recommend .3 mm vias on 1mm centers
as
thermal vias under the part, but as to any hard data on choice of solder,
heat profiles, or the like, I did not see any reliable data. They mentioned
the idea of plugging the vias or tenting them, and the use of no-clean flux
containing solders because there is no way you would be able to clean under
the part... That has me a little concerned too. I have heard of troubles
with plugging vias on this forum before... but if I leave them open won't
they will most likely wick the solder away from the pad to the far side of
the board starving the thermal pad.
I have used a chip with a 'belly thermal pad' before but in small
quantities... this is a medium volume product and troubles with assembly
could be costly so I value the comments put forth greatly.
Thanks again for your experienced insight.
Best regards,
Bill Brooks - KG6VVP
PCB Design Engineer, C.I.D.+, C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
Datron World Communications, Inc.
_______________________________________
San Diego Chapter of the IPC Designers Council
Communications Officer, Web Manager
http://dcchapters.ipc.org/SanDiego/
http://pcbwizards.com
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