Hi Bill;
If you don't mind, can you also forward me that technical sheet (I am
assuming it is a PDF doc).
Regards
TDK
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: Friday, December 02, 2005 9:59 AM
To: [log in to unmask]
Subject: Re: [TN] 56 pin LFCSP footprint
Thanks...
I contacted AD and talked with a technical support representative...
He's
looking into a footprint recommendation from their development team...
He
also sent me an application note on the part. It seems it has a large
thermal 'belly pad', for lack of a better name, that gets soldered to
the
board in the center of the part. They recommend .3 mm vias on 1mm
centers as
thermal vias under the part, but as to any hard data on choice of
solder,
heat profiles, or the like, I did not see any reliable data. They
mentioned
the idea of plugging the vias or tenting them, and the use of no-clean
flux
containing solders because there is no way you would be able to clean
under
the part... That has me a little concerned too. I have heard of troubles
with plugging vias on this forum before... but if I leave them open
won't
they will most likely wick the solder away from the pad to the far side
of
the board starving the thermal pad.
I have used a chip with a 'belly thermal pad' before but in small
quantities... this is a medium volume product and troubles with assembly
could be costly so I value the comments put forth greatly.
Thanks again for your experienced insight.
Best regards,
Bill Brooks - KG6VVP
PCB Design Engineer, C.I.D.+, C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
Datron World Communications, Inc.
_______________________________________
San Diego Chapter of the IPC Designers Council
Communications Officer, Web Manager
http://dcchapters.ipc.org/SanDiego/
http://pcbwizards.com
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