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December 2005

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Subject:
From:
Charlie McMahon <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Charlie McMahon <[log in to unmask]>
Date:
Wed, 21 Dec 2005 18:38:25 -0500
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text/plain (177 lines)
Hello Dwight:



Point taken based on the designs you routinely do.

The challenge now however is the no-lead factor and the lawsuits to come
when assemblies fail not in the field but at assembly. How to build in a
confidence factor is what I am concerned with. In my view, when failures
occur the first suspect will be the board fabricator and we need to do
change/improve how we specify materials in working with our partners to
ensure a quality result.



Options include coupons and/or production samples to be used by the assembly
house to prove out their process.

Those with BGA designs I would surmise would be even more concerned with
process/material control.



Thin core and micro via, buried and otherwise are not exotic applications to
me and I have been personally successful in meeting those challenges.
However, what is of concern to me and others will be the L-F effect on those
designs. Personally, I believe proposals from professionals like you on the
front lines of volume production will provide specific guidance on how to
adjust.

Does your company already perform lead free and if so, has your material
choice changed as well?

Do you utilize any coupons/sample assemblies prior to production release?
What would you suggest as a process protocol?



Your comments would be appreciated.



Charlie McMahon

McMahon Sales Company

P.O. Box 1024

Windham, New Hampshire  03087

Tel: 603-432-3111

Fax: 603-432-6854

Cell: 603-401-4646

e-mail: [log in to unmask]





-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Dwight Mattix
Sent: Wednesday, December 21, 2005 5:51 PM
To: [log in to unmask]
Subject: Re: [TN] ] Qualification of the Pb-free capable manufacturers



At 02:25 PM 12/19/2005, Valerie St.Cyr wrote:

>Charlie,

>

>My *OWN OPINION* is that there is no value for solder float which will be

>indicative of

>a laminate's ability to withstanding LF assembly in any and all PCBs that

>it might be

>fabricated into. Any temperature used would only be as a reference value.

>A PCB

>which is thin, has only single-sided assembly, and has low additional mass

>from the

>added components, does not need to have a very high solder float

>withstanding

>capability because the LF assembly temperature will be low, relatively

>speaking.



In the little twisted corner of the world I live in, solder floats are an

essential predictor of SMT reflow survival.  Longterm reliability is a

whole 'nother discussion.



This is especially true on our thinner boards. e.g. 8-10 layer stacked uvia

(built up boards) with single ply uVia layers, high buried via and uVia

density, via fill and a high percentage metallization.



We routinely produce designs in excess of 2000 vias/in^2 (>1500 uVias/in ^2

and >200 buried vias/in ^2) on a 1mm thick 8-10 layer.

Who needs a delam test vehicle?  Every build is an adventure.



dw



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