In a message dated 12/1/2005 3:02:32 PM Eastern Standard Time,
[log in to unmask] writes:
How will the boards be in the future?
Ingemar, your question can be answered by the roadmap activities by IPC,
iNEMI, and other world organizations such as JISSO in Japan. All of these
groups receive inputs from the ITRS (International Technology Roadmap for
Semiconductors - the home of "Moore's Law) and other sources. From that start, each
forecasts out about 10 years to what the best committee estimate is of
technology. Typically, there is a forecast for "state of the art" - the
computational example you cited, and for "revenue center of gravity" - what the average
board fabrication shop will be capable of.
There is new information out there right now - iNEMI released their roadmap
this past February, JISSO (only published in Japanese) came out in June, and
the IPC Roadmap is just now being sent to Official Representatives of member
companies. Contact me off line, and I can give you the ordering information
for any of these documents.
In addition, both IPC Works had, and IPC Apex/Expo will have three hour
"free forums" of what is contained in the IPC (and I think the iNEMI) roadmaps.
In case you think the Roadmap volunteers just lock themselves in a room and
drink lots of Mountain Dew before forecasting, the IPC Roadmap for 2005
contains confirmation of the revenue center of gravity numbers on line/space width,
drill diameter, controlled impedence capability, etc with the IPC's PCQRR
(Printed circuit Capability, Quality, and Relative Reliability) committee
sorting the information from about 140 worldwide board fabrication shops
Occassionally, we do go out on a limb. For instance, our board fab chapter
committee did forecast that the state of the art in chip mounting for 2015
would be some sort of "nano-velcro" to credit Motorola. At the recent IPC
Miniaturization conference held at Motorola, Iwanna Turlick of Motorola said that
our estimate of 10 years to implement that was too long. Can you imagine
this forum without any of the lead-free conversations??? Just put your silicon
on the substate, push down, and highly conductive carbon nanotubes keep it in
place, conduct electricity, and remove heat. Wow, talk about a
breakthrough!!!!
Denny Fritz
MacDermid, Inc
Chapter Editor - Organic Interconnection Substate Fabrication
IPC Roadmap.
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