Many thanks Leo.
joyce
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Leo Higgins
Sent: Wednesday, November 30, 2005 11:59 AM
To: [log in to unmask]
Subject: Re: [TN] blind build definition
Hi Joyce,
IC assembly and packaging of an unprobed wafer is called "blind-build",
so, as you note, the finished packaged devices will show higher yield loss
vs. testing of probed wafers.
Best regards,
Leo
Leo M. Higgins III, Ph.D.
Vice President Technical Support Operations
ASAT, Inc.
3755 Capital of Texas Highway, Suite 100
Austin, Texas 78704
ph 512-383-4593
fx 512-383-1590
[log in to unmask]
www.asat.com
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Joyce Koo
Sent: Wednesday, November 30, 2005 9:02 AM
To: [log in to unmask]
Subject: [TN] blind build definition
Guys and Gals,
could anyone define a term "blind build" of MFG lot for reliability test?
As my per my limited understanding, the "blind build" mean to be no
electrical test performed after the MFG, therefore, the yield data is part
of the initial assessment of yield upon recieving at the test facility
(doesn't matter if it is in house or external). However, someone point out
that "blind build" terminology implys that the test die (chip) is not probed
at the waffer supply (un-probed die), that means the initial testing will be
2 yields: the chip yield and assembly yield. Does any of your gurus can
tell me what is proper definition of "blind build"? Is there a official
definition? Thank you very very much. (I am not try to split hair...
please help me to define...).
Best regards,
jk
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