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November 2005

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Subject:
From:
Pete menuez <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Pete menuez <[log in to unmask]>
Date:
Tue, 8 Nov 2005 23:17:17 -0500
Content-Type:
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John,
We thermal cycle at similar conditions (typical for us is -55 / +70 c) but
I've done some testing at -65/ +100.  You should, in my opinion, expect good
results. (ie no plating cracks).

Worst case scenerio - Thick board, non functional pads removed, FR4
material.  With this set up you'll see a lot of Z axis
expansion/contraction.  If the plated copper is robust you will have a
better chance of survival.  If you have less robust copper you will have
failures. Other criteria is important - hole size, Tg of material and
more...

Two fixes come to mind. Work with the board fabricator. If they can improve
there plating that may be all that is necessary. Or internally you could
have your designers add the non functional pads back into the board....

good luck

Pete




>From: Babcock John <[log in to unmask]>
>Reply-To: TechNet E-Mail Forum <[log in to unmask]>,              Babcock John
><[log in to unmask]>
>To: [log in to unmask]
>Subject: [TN] Temperature Cycling
>Date: Mon, 7 Nov 2005 16:29:08 -0800
>
>Does anybody know of any special considerations on circuit boards for
>temperature cycling.  We are testing the board to -65C to +85C.  We are
>seeing via barrels cracking and TH connector solder joints cracking.  Do
>we need to add extra pad area?  Just curious if there is an IPC document
>on cold temperatures or temp. cycling and causing stress on the circuit
>boards.
>
>Thanks!
>
>John Babcock
>
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