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Date: | Mon, 7 Nov 2005 19:44:33 -0500 |
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John,
I'm not sure of an IPC document but we perform HALT from -30C to +80C.
If you go too cold or hot you defeat the purpose of HALT by inducing
catastrophic failure unless you are performing a destructive test. Where
did you get the data that led you -65C to +85C testing?
Barrie Fraley
EMC Corp
DVT/HALT
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Babcock John
Sent: Monday, November 07, 2005 7:29 PM
To: [log in to unmask]
Subject: [TN] Temperature Cycling
Does anybody know of any special considerations on circuit boards for
temperature cycling. We are testing the board to -65C to +85C. We are
seeing via barrels cracking and TH connector solder joints cracking. Do
we need to add extra pad area? Just curious if there is an IPC document
on cold temperatures or temp. cycling and causing stress on the circuit
boards.
Thanks!
John Babcock
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