IBM wrote a paper on the eless Ni/eless Pd/immersion Au (ENi/EPd/IAu) based
upon the use of an Atotech system in 1999. Results were generally favorable
for Au wire bonding, soldering (SnPb solder), and for use as a pad finish
for a socketed LGA. Said to keep Pd less than approx 10-11 microinches to
avoid a Pd-Sn IMC layer at the interface of the solder and pad. Here is the
web link:
http://www-3.ibm.com/chips/micronews/vol5_no4/memis.html
If the link works it will take you to the IBM publication as shown below:
MicroNews
Fourth Quarter 1999, Vol. 5, No. 4
Enabling Grid Array Modules Through Advanced Printed Wiring Board Surface
Finish
Irving Memis
I have pasted the article here, but could not get figures to copy.
Enabling Grid Array Modules Through Advanced Printed Wiring Board Surface
Finish
Irving Memis
Abstract
As silicon technology advances, the trend is to increase the use of area
array packages. Each of the different area array packages drives different
requirements on the printed wiring board (PWB) for surface finish and
assembly. Ball grid array (BGA) and column grid array (CGA) packages have
driven a need for coplanarity not seen before in other surface mount
technology (SMT) packages that could not necessarily be accommodated by the
solderable surfaces in use. This has required a surface on the PWB, such as
an organic surface preparation or gold, to assure solderability and to
maintain a coplanar surface. Although gold is suitable, if it is used
throughout the part, it causes concerns in SMT soldering due to
embrittlement. As I/O requirements and the use of flip chip have increased,
BGA and CGA packages become less compatible for assembly (distance from
neutral point (DNP), etc.) and land grid array (LGA) packages have become a
necessity. This has driven another set of attachment requirements for the
surface of the PWB to allow for attachment of an LGA socket for which
solderable gold or other surfaces may not be suitable.
In addition, direct chip attach (DCA) will come to the forefront, and its
requirements vary with the use of wire bond (WB) or flip-chip attach (FCA).
These surfaces are also unique in their requirements for attachment to the
organic interconnect technology.
Along with all the area array requirements, designers still need the
flexibility to use plated through hole (PTH) and standard SMT to meet
function and design. With such disparate requirements in surface finish on
the PWB, the impact of using advanced packaging can drive complexity into
the PWB and create program cost problems for the designer. What is needed,
therefore, is a singular conformal surface finish that allows for all types
of attachment.
This paper defines the use of a surface metallurgy that is widely available
in the industry, but in disparate applications. This metallurgy can be used
in a conformal application and will be shown to fulfill the needs of varying
methods of attach. Consideration of all the designs and variations will be
given, showing the impact of this single conformal surface metallurgy.
Individualizing, or selectively plating PWBs will be presented as
methodologies to contain program costs. Further, consideration will be given
to compare this conformal surface metallurgy to current surfaces, noble
metals, such as gold, or organic surface preparations, to maintain a
perspective on use.
As advancement of modules continues to drive density of connection to the
PWB a surface finish that is compatible over a wider spectrum is needed to
maintain parallel capability. Specific treatment of real time applications
will allow for understanding of how to use this surface.
Introduction
The use of nickel-gold (Ni-Au) surface finish in the chip carrier industry
has a long history. The coating commonly consists of an outer layer of soft
gold (0.61.0 microns or 2540 microinches) over a diffusion barrier layer
of nickel (25 microns or 80200 microinches). The nickel layer serves as a
barrier to out-diffusion of copper from the underlying copper pads and
provides a mechanically robust, hard substrate to facilitate wire bonding to
the soft gold surface. However, Ni itself can diffuse out through the Au
layer and degrade wire bondability. Therefore, the Au layer has to be
relatively thick (2540 microinches) and non-porous. The Ni and Au layers
can be deposited by either electrolytic or electroless plating over a
laminate chip carrier circuit. Despite having some drawbacks, electroless
plating, is particularly simple since it can be deposited only on the
exposed Cu features after solder mask patterning. However, not all solder
masks are compatible with the harsh Ni and Au electroless baths. That is why
nickel-gold plating is sometimes applied before solder mask application.
Most electroless Ni plating systems use hypo-phosphite baths and co-deposit
612% phosphorus in the Ni layer. Also, one common method of depositing an
electroless nickel/electroless gold coating is to first deposit electroless
Ni, then give it a strike of immersion Au (24 microinches), and then plate
electroless Au. Sometimes, the plating is denoted as Eni/Iau/EAu. This
thick, soft gold surface finish is currently the standard finish for
fabrication of single-chip modules, which are known by various names such
as: SCM-L, WB-plastic ball grid array (PBGA), or simply PBGA. The coating
shows very good performance in gold wire bonding and acceptable performance
for solder reflow attachment of BGA balls.
Driven by the need of higher functionality and smaller form factor,
increasingly complex packaging structures are evolving that are pushing the
SCM-L toward the multi-chip module (MCM-L). An MCM-L may contain one or more
wire bonded chips together with flip chips soldered to the carrier by the
C-4 method, packaged chips in quad flat pack (QFP) and BGA formats, and
other SMT components-decoupling capacitors, connectors, and the like-also
soldered to the board [1]. The MCM-L package itself may be constructed as a
BGA, in which case, solder balls will be attached to one side of the MCM-L
for eventual mounting to the next level of packaging. The wire bondable
Ni/thick Au finish is not suitable for soldering of SMT and BGA devices
because the amount of Au (2540 microinches) is high enough to adversely
affect the ductility, interfacial strength, and ultimately the reliability
of solder joints of the critical BGA and SMT devices. Although it might be
thought that a solution is to use a thinner gold layer, such as that
deposited by immersion Au plating, that would be unsuitable for wire
bonding. Another solution, and this approach is sometimes used, is to
deposit Ni/thick Au selectively on the wire bond pads and temporarily mask
the SMT and BGA features. Finally, after the mask is removed, the Cu
features are given an organic solderability preservative (OSP) treatment.
OSP's form a thin invisible organic complex with Cu, prevent its oxidation,
and maintain solderability. The materials, process complexities, and
controls required for selective masking and plating makes this a costly
proposition. What is needed for this type of mixed or hybrid assembly is a
surface finish that is both wire bondable and solderable.
The same need for a versatile surface finish that can be applied over the
entire surface after solder mask patterning also arises for printed circuit
cards and boards. Advanced printed circuit boards may use soldered
components, land grid array (LGA) modules, and compliant pin (or forced-fit)
connectors. LGA modules are essentially BGA modules without the solder
balls. They are not soldered to the board. Instead, electrical connection is
established through pad-to-pad contact by mechanically clamping the board
and the LGA with an intervening metallized interposer. While Ni/thick Au
would be a good surface finish for the LGA and compliant pin connector, it
is not so for the soldered components. Conversely, an OSP coating would be
unsuitable for LGAs.
A palladium (Pd)-based surface finish is considered to have the best
potential for meeting the requirements of wire bonding, solderability, and
LGA connector applications and has received a lot of attention in the
industry [2,3,4]. Several suppliers have developed plating chemistries for
electroless deposition of Pd. The coating typically consists of 830
microinches electroless Pd deposited either directly over Cu or over a first
layer of electroless Ni (80200 microinches). The Pd layer is then coated
with a very thin layer of immersion Au (0.41.2 microinches). The Au layer
provides passivation for Pd. Bare palladium is prone to absorbing
contaminant species from the environment, which may compromise its
performance as a surface finish.
An electroless Pd plating [5], referred to as a universal finish by its
supplier, Atotech, has been installed in IBM Endicott, NY and is under
evaluation. The plating process has been optimized for depositing any
selected thickness of Pd on solder mask-patterned chip carrier laminates and
printed circuit cards and boards. The performance of the finish has been
evaluated for wire bondability, solderability, and LGA interconnection and
is the subject of this paper. So far, all of the studies have been carried
out with a version of the coating with a Ni underlayer (i.e., ENi/EPd/IAu).
Wire bondability has been evaluated by standard wire pull and failure mode
studies. LGA interconnection evaluation consisted of measuring the initial
resistance and change in resistance as the LGA/board assembly was subjected
to various mechanical and environmental stresses. Solderability of the
coating was evaluated by ball shear testing and by cross-sectioning of SMT
and BGA components attached to circuit boards by solder paste reflow.
Thermal cycling evaluation of long-term reliability of SMT/BGA components
and wire bond product will be carried out in the future. The compatibility
of forced-fit connectors with the Pd-based board coating will also be
studied in the future.
Process Description
The process described below is what is referred to as the universal finish
by Atotech. Up through electroless Ni deposition, the process is consistent
with typical mid phosphorus electroless nickel systems in the industry
today. Following Ni deposition, an electroless Pd and immersion Au layer is
deposited. Pd is denser than Au and a better diffusion barrier, therefore
the Pd deposit can be thinner than Au and provide similar protection. The
thinner Pd is favorable for minimizing its impact when it dissolves in
eutectic solder for SMT or FCA use.
The overall process sequence that is used is shown in Figure 1. Differences
in Pd thickness are obtained by varying the dwell time in the electroless Pd
solution.
Figure 1. Process sequence.
The reactivator step has recently been modified to improve Ni/Pd
metallurgical adhesion and reduce oxidation of the Ni surface prior to Pd.
Both no reactivator and new Atotech reactivator (Ni complexor) dramatically
improved wire bond pull test mechanism (bond peels eliminated) as well as
improved ball shear performance (interfacial failure mode reduction). New
Atotech reactivator has been incorporated due to its ability to reactivate
Ni if an unexpected machine delay occurs.
Figure 2. Processing ranges.
The palladium deposition rate of 1.5 microinches/min can be varied by
adjusting any of its operating parameters. For the referenced testing, all
parts have been processed within the ranges shown in Figure 2.
Pd thickness is measured in conjunction with Ni using a Fischerscope(tm)
X-Ray fluorescence tool (system XDVM). Also to be noted are variations in
pretreatment dwell times. Again, these are due to variations in the incoming
surface prior to ENi/EPd/IAu, which depend on the product offering. The two
most important offerings are as follows:
1. Selective plating using dry film resist layer prior to plating. This
allows the use of OSP for SMT features.
2. Plating using solder mask prior to plating. All exposed metallurgy
as defined by the solder mask will have the universal finish.
Dwell time considerations include pitch of device (Ni spacing optimization)
and potential residue removal, which depends on the product offerings noted
above.
Wire Bond Performance
Industry standard wire bond with gold ball bonding uses a finish of soft
gold over nickel. The measure of goodness of the surface is a consistently
acceptable wire pull strength with a low standard deviation and absence of
interfacial failure modes, such as wire lifts. The universal finish was
compared with the industry standard electroless gold on several occasions by
IBM and also by potential customers. The results have been consistently
favorable with the universal finish having slightly higher minimum and
average pull strengths. There were no unacceptable failure modes with either
finish.
To examine the robustness of the universal finish, an additional test cell
was added where-in addition to normal die attach-a one-hour bake at 150° C
was added. The thicknesses were 150 microinches Ni with 15 microinches Pd
and 1.2 microinches immersion Au in the Pd cells and 150 microinches Ni with
35 microinches electroless Au and 4 microinches immersion Au for the Au
cells. A Hughes 2460-5 bonder with fixed force, time, and power settings was
used to bond 1.25 mil gold American fine wire with a Gaiser 1551-16-437GM
capillary. Figure 3 shows the typical performance on IBM Driclad(tm) FR4
laminate, which has a 170° C glass transition temperature, with 10 test cell
replications with 40 test pulls per cell. This gives a total of 400 test
pulls per treatment. The data is reported for each group of 40 samples and
the ranges represent the highs and lows of the 10 test cells. The mean for
each cell (XBar) standard deviation (SD) were derived from the 40 points in
each cell. Xbar-3xSD is a projection of the expected low point at three
standard deviations below the mean. The low value is the actual low pull of
each cell.
Additional wire bond data comparing the same finish variations has been
gathered on IBM Surface Laminar Circuit(tm) (SLC) [6] microvia product,
which has no glass reinforcement in the outer layers and a glass transition
temperature of 120° C. The same bonding system was used. Wire bonding
conditions were optimized around this material, and results were similar to
the IBM Driclad results. The conclusions on the surface finish equivalence
is the same, and a sample of that data for five test cells of 40 samples
each is noted in Figure 4.
Figure 3. Wire bond pull strength (grams) for 1.25 mil gold ball bonds on
IBM Driclad.
Figure 4. Wire bond pull strength (grams) for 1.25 mil gold ball bonds on
IBM SLC.
The excellent wire bond performance of the Pd universal finish is very
valuable for MCM-L applications, because the electroless Pd can be
selectively plated using standard aqueous resists to allow the SMT pads to
be protected from plating and have a standard OSP surface for the SMT pads.
A further cost saving potential is to plate Pd on both the wire bond and SMT
pads and eliminate the need for selective plating. This will be covered in
the SMT solderability section of this paper.
Land Grid Array Applications
One of the new innovations in area array sockets is the land grid array
(LGA) connector. IBM has tested 1-mm I/O pitch Thomas & Betts MPI/LGA(tm)
sockets with a variety of PWB pad plating metallurgies. These sockets use a
proprietary flexible conductive polymer with embedded metalized particles.
The material is molded into small columns in a polyimide carrier. The
carrier is used within the socket as an interposer between the LGA module
and the PWB.
PWB test vehicles were made with three different pad platings as indicated
below:
1. Hard gold (HG): 30 microinches electrolytic hard gold over 75
microinches electrolytic Ni.
2. Pd: 100 microinches electroless Ni, 5 to 10 microinches electroless
Pd and 1 to 2 microinches immersion Au.
3. Immersion gold (IM): 100 microinches electroless Ni and 3 to 4
microinches immersion Au.
The hard gold plating is fairly standard in the industry. However, it was
believed Pd plating would also be suitable for use with this LGA connector.
In some cases, testing was done with several thicknesses of Pd to see if
there was a lower limit from a reliability standpoint. Test cards were also
made with immersion gold over nickel, because a set of prototype cards was
accidentally made with this metallurgy and the information would be useful
to check the robustness of the connector system. The immersion gold finish
is not practical for production use because it will allow nickel corrosion
products to form on the surface, but could be useful for prototypes.
The following data summarizes the change in average contact resistance
readings for each of the various test conditions as a function of the test
parameters noted in Figure 5. Durability is the sequence of removing and
reinserting. The three finishes described above-HG, Pd and IM-were in each
cell, and the differences in performance among the three finishes was small.
Figure 6 shows the maximum observable change in contact resistance through
the entire test duration of each test. The largest observable positive
change was in the 55° C temperature life test, and in that test the Pd
finish was 2 milliohms better, but all finishes stayed within the allowable
maximum of 10 milliohms. The higher change in this test is possibly due to
material property changes in the interposer at 55° C. A future test at 40°
C is planned to see if the effect is reduced. Pd is equal to or better than
HG for all the tests and can therefore be used with high confidence for this
connector system,The data in Figure 6 is all at 510 microinches of Pd.
Additional tests with the same connector system were run at Pd thicknesses
of 15, 25, and 45 microinches.
Figure 5. Test parameters used for LGA connector evaluation.
The parameters used are shown in Figure 7, which details the two test
sequences.
Figure 8 shows the data for the various Pd thicknesses. All of the Pd
thicknesses were acceptable to 10 milliohm maximum change. This gives good
latitude for optimizing Pd thickness for minimum cost and to meet the
requirements of the SMT devices.
Figure 6. Contact resistance maximum change milliohms) for three surface
finishes with the parameters in Figure 5.
SMT Solderability
Solderability has been evaluated by reflowing 0.025-inch diameter eutectic
Sn/Pb solder balls on ENi/EPd/IAu coated chip carrier Cu pads, followed by
ball shear testing. Molten solder dissolves the immersion Au and Pd layers
and disperses the gold-tin (Sn) and Pd-Sn intermetallics into the bulk of
the molten solder ball. Solder bonding takes place essentially between Sn
and Ni.
Figure 7. Test parameters used for LGA connector evaluation for various Pd
thicknesses.
If the Pd thickness is too high (>1520 microinches), incomplete dispersal
of Pd-Sn intermetallics would result, and residual intermetallics near the
nickel-solder interface would tend to cause brittle fracture. In ball shear
testing, brittle fracture of the solder joint is sometimes seen when the Cu
pad is coated with electroless Ni and a precious metal such as Au or Pd.
Several mechanisms have been proposed [3,7,8] to explain this phenomenon,
chief among them being residual intermetallics near the interface and
oxidation or corrosion of the underlying Ni surface, leading to a loss of
solder wettability. The interfacial failure mode is characterized by a flat,
planar fracture surface at the Ni layer rather than fracture occurring
throughout the solder. In our studies, it was found that a very high
percentage of interfacial fractures resulted when the electroless Ni layer
was reactivated or prepared for subsequent Pd plating by using the original
reactivator suggested by the plating supplier. The interface failure
incidence decreased markedly when a new reactivator was used or when the
reactivation step was skipped and time delay between Ni and Pd plating was
minimized. Ball shear data for various ENi/EPd/IAu cells are given in Figure
9, which shows the average of 24 balls per cell.
So far, electroless Pd thicknesses up to 11 microinches have been ball shear
tested. This range will be extended to 20 microinches in the future.
In addition to ball shear testing, several types of surface mount components
were attached by standard solder paste reflow to printed circuit boards,
which had their pads coated with ENi (150 microinches)/EPd (15
microinches)/IAu (1.2 microinches). Components included quad flat pack
(QFP), PBGA, and ceramic BGA (CBGA). The solder joints were cross-sectioned
and metallographically inspected (Figures 1013). Solder wetting and joint
formation appear to be normal, with no evidence of voids or undissolved Pd.
As expected, solder joint formation takes place between Sn from the solder
and the Ni layer of the coating. The extent of metallurgical reaction
between Sn and Ni is very small, however; the original thickness of Ni
remains virtually unaltered. The long-term reliability of solder joints is
customarily evaluated by their ability to survive a sufficient number of
thermal cycles. In the future, accelerated thermal cycling (ATC) evaluation
of SMT and BGA solder joints on the universal finish will be carried out.
Figure 10: Cross-section of a solder joint formed between a QFP lead and a
Pd-coated card pad (the pad is at the bottom side in each micrograph).
Figure 11: Cross-section of PBGA solder joint
Figure 12: Cross-section of CBGA solder joint
Figure 13: Higher magnification micrograph of a solder joint.
Summary
The universal finish process has been successfully installed and
investigated in all the planned applications: wire bond, land grid array
connectors, and SMT soldering. It performed well in all three areas and can
enable MCM-L and land grid array board applications. Additional reliability
data is underway to complete the data base.
References
[1] Giuseppe Vendramin, Michael Weller, "MCM-L: Rethinking Electronic
Packaging MCM-L", Proceedings of the Technical Program, Semicon West '98,
San Jose, CA, July 1998.
[2] A. Genovese, S. Oggioni, F. Zambon, "Is Palladium Finishing a Real
Enabler in the Hybrid MCM-L PBGA Module Arena?". Proc. of 1999 Int. Conf. on
High Density Packaging and MCMs, Denver, CO, 1999:64-69.
[3] R.W. Johnson, M. Palmer, M. Bozack, T. Isaacs-Smith, "Thermosonic Gold
Wire Bonding to Palladium Finishes on Laminate Substrates," Proc. of 1998
Int. Conf. on Multichip Modules and High Density Packaging, Denver, CO,
April 1998:291-299.
[4] B. F. Stacy et al, "Palladium for PWB Applications," Proc. of Nepcon
(West and East), Vol. 3, 1997:1569-1578.
[5] H. Mahlkow, "Electroless Palladium - A New Final Finish for Printed
Circuit Boards," Proc. of Printed Circuit World Convention VII, Basel,
Switzerland, May 1996:005/1-2.
[6] R. Carpenter and I. Memis, "SLC: An Organic Packaging Solution for the
Year 2000," Proceedings of the Technical Program, Nepcon West '96, February
1996:1469-1479.
[7] J. Glazer, P. A. Kramer, J. W. Morris,Jr.,"Effect of Au on the
Reliability of Fine Pitch Surface Mount Solder Joints," Circuit World, Vol.
18, No. 4, August 1992:41-46.
[8] Zequn Mei, Patrick Calley, "Mechanical Reliability and Failure Analysis
of Mid-Range BGA Packages Soldered on Electroless Ni/Immersion Au and
Organic Coated Cu," Proc. of 9th. Symposium on Mechanics of Surface Mount,
ASME Annual meeting, November 1997.
Acknowledgments
Acknowledgment to George C. Haddon Jr., who initiated the technical paper
and abstract on this subject and brought the team together for this
publication; and to the team members, John Konrad, John Lauffer, Mike
Lemmon, James Stack, Roy Magnuson, Dan Massey, Mark Plucinski, and Amit
Sarkhel for their contributions to this paper.
Irving Memis has held managerial and engineering positions relating to
electronic packaging and interconnection including process development,
reliability, manufacturing engineering, and quality assurance. Product
involvement includes ceramic chip carriers, plastic chip carriers, printed
wiring boards, back panels, and card assembly. He is currently a product
manager with IBM Microelectronics, Endicott, NY.
A version of this paper was presented at the 2nd Annual Semiconductor
Packaging Technologies Symposium SEMICON West '99, July 14, 1999, San Jose,
CA.
For information on IBM Field Design centers or to locate one near you,
visit:http://www.chips.ibm.com:80/bluelogic/engineering/For more information
about Destiny Technology, visit:http://www.destiny.com.tw/
Best regards,
Leo
Director of Applications Engineering
ASAT, Inc.
3755 Capital of Texas Highway, Suite 100
Austin, Texas 78704
ph 512-383-4593
fx 512-383-1590
[log in to unmask]
www.asat.com
The information contained in this electronic message is CUSTOMER/SUPPLIER
PRIVILEGED AND CONFIDENTIAL INFORMATION intended only for the use of the
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intended recipient, you are hereby notified that any dissemination,
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you have received this communication in error, please immediately notify the
sender by electronic mail. Thank you.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Ray, Carl (GE
Infrastructure)
Sent: Thursday, October 27, 2005 8:22 AM
To: [log in to unmask]
Subject: Re: [TN] ENIG and brittleness
I got one for you guys....... I have a board house who claims to have
created a process the eliminate the "Black Pad" issue while decreasing the
gold brittle issues of ENIG finishes. They claim a thin layer of Palladium
between the gold and nickel does the trick... I am not familiar with this
process and have requested more data from the board supplier to support
their claims.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Werner Engelmaier
Sent: Wednesday, October 26, 2005 11:25 PM
To: [log in to unmask]
Subject: Re: [TN] ENIG and brittleness
Hi Eddie,
You will not find such information.
First, while ENIG can lead to brittle interfacial separations, it does not
lead to brittle solder joints--as in 'gold embrittlement.' the difference is
in
the failur mode, the separation would be at the Ni/Ni-IMC interface, not the
solder per se.
Second, while some people claim to have suppliers who do not produce ENIG
suffering from 'Black Pad' brittle interfacial separations, many reports of
ENIG-'Black Pad' failures are documented.
Thus, the real question is why is your customer looking to convert to ENIG,
and what is he converting from?
Regards,
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737, Cell: 386-316-5904
E-mail: [log in to unmask], Website: www.engelmaier.com
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