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October 2005

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Subject:
From:
Jeffrey Bush <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Jeffrey Bush <[log in to unmask]>
Date:
Thu, 20 Oct 2005 08:14:01 -0400
Content-Type:
text/plain
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text/plain (186 lines)
I think the assumption in # 1 may need further consideration.  The
thermal conductivity of Ag/Cu fills are ~ 5w/mk, quite a bit higher than
a via-in-pad epoxy fill.  The device may need this level of cooling to
maintain operational temperatures.     

Jeffrey Bush
Director, Quality Assurance and Technical Support

VERMONT CIRCUITS INCORPORATED
  76 Technology Drive - POB 1890
    Brattleboro, Vermont 05302
      Voice: 802.257.4571.21 Fax: 802.257.0011
           http://www.vtcircuits.com
 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Wee Mei
Sent: Thursday, October 20, 2005 4:41 AM
To: [log in to unmask]
Subject: Re: [TN] Delamination at Thermal Via area?

Re: [TN] Delamination at Thermal Via area?Steve,

I was told that the vias are silver epoxy filled. It was bake at 125
degree C for 8hr before going through the reflow.

The same process is repeated on another piece without the component this
morning. It was bake and after the first reflow cycle, the thermal via
images can be seen. When it was put through another reflow cycle, the
same defect can be seen on both sides of the board at that location.

Reading from the responses so far, can I conclude with the followings :

1. There is no need to have filled thermal via as long as there is a
matrix of them provided.
2. If filled thermal via is used, the temp profile has to work out to
take the filled material property into consideration.
3. While a large piece of thermal pad can be provided on the component
side to provide close contact with the component for better heat
dissipation, no thermal pad should be used on the bottom side of the
board. This will provide an escape route for trapped air if any from the
filled thermal via to outgass.

A BIG THANKS to all. I have learned from all of you.

Regards,
Wee Mei
  ----- Original Message ----- 
  From: Stephen R Gregory 
  To: TechNet E-Mail Forum ; Wee Mei 
  Cc: [log in to unmask] 
  Sent: Wednesday, October 19, 2005 10:29 PM
  Subject: Re: [TN] Delamination at Thermal Via area?


          Hi Wee Mei!

          I've got your pictures posted. Go to:

          http://www.stevezeva.homestead.com/files/U2_top.JPG

          http://www.stevezeva.homestead.com/files/U2_bottom.JPG

          http://www.stevezeva.homestead.com/files/U2_delamination.JPG

          Are the vias filled? Are you seeing this delamination on very
many

          PCB's? Are you seeing it only on the bottom of the PCB?

          Kind regards,

          -Steve Gregory-

          Senior Process Engineer

          LaBarge Incorporated

          Tulsa, Oklahoma

          (918) 459-2285

          (918) 459-2350 FAX






          Wee Mei <[log in to unmask]>

        Sent by: TechNet <[log in to unmask]>

        10/19/2005 03:47 AM

        Please respond to TechNet E-Mail Forum <[log in to unmask]>; Please
respond to Wee Mei <[log in to unmask]>

                        

          To:     [log in to unmask]@SMTP@Exchange

          cc:     (bcc: Stephen R Gregory/LABARGE)

          Subject:        [TN] Delamination at Thermal Via area? 


          Hello,

          Just asked Steve to download 3 pictures on the defects. Kindly
take a look

          at them and would appreciate some feedback on the possible
root cause.

          Steve : Thanks for the downloading.

          Regards,

          Wee Mei

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