Amen, problem solved.
In addition, there is slight dishdown in the fill planarization. A perfectly
planar surface is preferred.
Dave Simonik
Process Tech.
Sanmina SCI Corp.
Owego NY division
-----Original Message-----
From: Jeffrey Bush [mailto:[log in to unmask]]
Sent: Thursday, October 20, 2005 7:28 AM
To: [log in to unmask]
Subject: Re: Delamination at Thermal Via area?
To combat this type of issue, we have implemented a panel flash after 2nd
deposition to ensure the fillet was sealed - particularly important with
silver/copper epoxy fillers as the dep can be spotty and the
plating does not adhere to the epoxy.
Jeffrey Bush
Director, Quality Assurance and Technical Support
VERMONT CIRCUITS INCORPORATED
76 Technology Drive - POB 1890
Brattleboro, Vermont 05302
Voice: 802.257.4571.21 Fax: 802.257.0011
http://www.vtcircuits.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Leo Higgins
Sent: Wednesday, October 19, 2005 4:24 PM
To: [log in to unmask]
Subject: Re: [TN] Delamination at Thermal Via area?
Hi Steve,
I have enclosed two photos of a delam between the copper plated over
the top of a filled via in a double sided PCB substrate for a flip chip fine
pitch BGA. Hopefully you can post on your site. The substrate is approx
200um thick. The vias are not via-in-pad for flip chip solder ball attach.
The solder balls are attached just adjacent to these filled vias. Via
filling is insulative. You can see that the vias delaminated at some point
before the flip chip underfill cured since it is thinner directly over the
delam area. Since the via fill should be totally encapsulated by copper due
to the via sidewall plating and the copper plating over the fill, we suspect
the fill was not fully off-gassed and blew its lid with PbFree FC attach.
Thanks.
Best regards,
Leo
Director of Applications Engineering
ASAT, Inc.
3755 Capital of Texas Highway, Suite 100
Austin, Texas 78704
ph 512-383-4593
fx 512-383-1590
[log in to unmask]
www.asat.com
The information contained in this electronic message is CUSTOMER/SUPPLIER
PRIVILEGED AND CONFIDENTIAL INFORMATION intended only for the use of the
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Steve Gregory
Sent: Wednesday, October 19, 2005 12:49 PM
To: [log in to unmask]
Subject: Re: [TN] Delamination at Thermal Via area?
Hi George!
Got your pictures up! Check out:
http://www.stevezeva.homestead.com/files/Delamination_Blisters-1.jpg
http://www.stevezeva.homestead.com/files/Delamination_Blisters-2.jpg
http://www.stevezeva.homestead.com/files/Delamination_Blisters-3.jpg
Kind regards,
-Steve Gregory-
Senior Process Engineer
LaBarge Incorporated
Tulsa, Oklahoma
(918) 459-2285
(918) 459-2350 FAX
|---------+---------------------------->
| | "Wenger, George |
| | M." |
| | <George.Wenger@an|
| | drew.com> |
| | |
| | 10/19/2005 11:00 |
| | AM |
| | |
|---------+---------------------------->
>-----------------------------------------------------------------------
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-----------------------------------|
|
|
| To: TechNet E-Mail Forum
<[log in to unmask]>@SMTP@Exchange,
Stephen R Gregory/LABARGE@LABARGE |
| cc:
|
| Subject: RE: [TN] Delamination at Thermal Via area?
|
>-----------------------------------------------------------------------
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Wee Mei,
I've asked Steve to post three images of delamination blistering that might
be different than you are seeing but the cause is most likely the same. I
do not know how many layers there are or the number of thermal vias there
are in the heat spreader portion of the U2 footprint on your board but it
appears that your delamination is occurring in an area of the board where
the outside layers are totally covered by metal (i.e., copper). This is
decrease the ability of the board to outgas in those areas if the board is
heated too rapidly or to too high a temperature. I'm also assuming but can't
tell because I haven't seen a cross section of your thermal vias but my
guess would be that you do not have good attachment integrity of the
outer-layer copper to the barrels of the thermal vias and therefore the
thermal vias are not providing any mechanical strength to hole you board
together when reflowed. The three images I've sent to Steve show
delamination blisters on the bottom side of a 14-Layer PCB. The
delamination is occurring between layer 13 and layer 14 in areas that have a
copper ground plane on Layer 14. There acre also not PTH's in these areas
to hold the board together when internal moisture is driven off too fast.
There are no blisters where ever there are PTH's. We're not sure there was
a single cause for our delamination or multiple causes. These boards were
over 1 year old and could have and probably did absorb moisture from the
environment. We believe the reflow profile that caused these blisters had
too fast a ramp and too hot a peak temperature. If we baked the boards
prior to the reflow they didn't delamination or if we didn't bake the boards
and used a correct profile they didn't blister. I hope this information
helps you find the root cause for you delamination. My suggestion is to
examine your reflow profile and cross section thermal vias in the blistered
area.
Regards,
George
George M. Wenger
Reliability / FMA Engineer
Base Station and Subsystems Group
Andrew Corporation, 40 Technology Drive, Warren, NJ 07059 (908) 546-4531
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
Sent: Wednesday, October 19, 2005 10:30 AM
To: [log in to unmask]
Subject: Re: [TN] Delamination at Thermal Via area?
Hi Wee Mei!
I've got your pictures posted. Go to:
http://www.stevezeva.homestead.com/files/U2_top.JPG
http://www.stevezeva.homestead.com/files/U2_bottom.JPG
http://www.stevezeva.homestead.com/files/U2_delamination.JPG
Are the vias filled? Are you seeing this delamination on very many PCB's?
Are you seeing it only on the bottom of the PCB?
Kind regards,
-Steve Gregory-
Senior Process Engineer
LaBarge Incorporated
Tulsa, Oklahoma
(918) 459-2285
(918) 459-2350 FAX
|---------+---------------------------->
| | Wee Mei |
| | <[log in to unmask]
| | SG> |
| | Sent by: TechNet |
| | <[log in to unmask]>|
| | |
| | |
| | 10/19/2005 03:47 |
| | AM |
| | Please respond to|
| | TechNet E-Mail |
| | Forum |
| | <[log in to unmask]>|
| | ; Please respond |
| | to Wee Mei |
| | <[log in to unmask]
| | SG> |
| | |
|---------+---------------------------->
>-----------------------------------------------------------------------
---------------------------------------|
|
|
| To: [log in to unmask]@SMTP@Exchange
|
| cc: (bcc: Stephen R Gregory/LABARGE)
|
| Subject: [TN] Delamination at Thermal Via area?
|
>-----------------------------------------------------------------------
---------------------------------------|
Hello,
Just asked Steve to download 3 pictures on the defects. Kindly take a look
at them and would appreciate some feedback on the possible root cause.
Steve : Thanks for the downloading.
Regards,
Wee Mei
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