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| Reply To: | TechNet E-Mail Forum < [log in to unmask]>, [log in to unmask][log in to unmask]] On Behalf Of Franklin Asbell Sent: Wednesday, October 05, 2005 11:05 AM To: [log in to unmask]Subject: [TN] New IPC email forum With a show of hands (yes, we can see you) how many out there would be interested in subscribing to an IPC email forum for pcb (rigid, flex, rigid-flex, hi-rel, mil, etc) fabrication topics. [...]47_5Oct200511:13: [log in to unmask] |
| Date: | Wed, 19 Oct 2005 19:40:58 EDT |
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Hi Leo,
I am afraid you might be stuck with (2); for 2 reasons.
(1) I do not see 'resin recession' in either via barrel walls [IPC documents
except after soldering processes] ir burried (thermal) vias as a reliability
risk--where is the risk?;
(2) no matter what you do, the adhesion will likely never be enough; you
could fill the filling resin more to get its CTE closer to Cu.
Werner
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