Substrate is simple double sided BT-glass substrate. As I mentioned in my
first note, the delam had to occur prior to the underfill cure, but this
leaves a few different opportunities. The initial assessment was that the
product failed during MSL testing, but the thinner underfill over the delam
showed this was not true. So we too agree the delam was due to some gas
pressure in the filled via. Perhaps the via fill absorbed water during the
processes to plate the Cu cap over the via. Perhaps the via fill was not
fully cured. Or, maybe the via fill was not compatible with the flip chip
assembly reflow process. If any of these possibilities are true, and if the
via is 'hermetically' sealed by via sidewall Cu and the Cu caps, a prolonged
bake at 125 or 150C would not be expected to be effective in preventing the
delam during subsequent higher temp excursions for flip chip solder reflow
or underfill cure. Since a substrate bake before flip chip assembly, and
after FC assy but before underfill dispense, are standard processes, it is
possible that these 150C bakes caused the delam....
Best regards,
Leo
Director of Applications Engineering
ASAT, Inc.
3755 Capital of Texas Highway, Suite 100
Austin, Texas 78704
ph 512-383-4593
fx 512-383-1590
[log in to unmask]
www.asat.com
The information contained in this electronic message is CUSTOMER/SUPPLIER
PRIVILEGED AND CONFIDENTIAL INFORMATION intended only for the use of the
individual or entity named above. If the reader of this message is not the
intended recipient, you are hereby notified that any dissemination,
distribution and copying of this communication is strictly prohibited. If
you have received this communication in error, please immediately notify the
sender by electronic mail. Thank you.
-----Original Message-----
From: Dwight Mattix [mailto:[log in to unmask]]
Sent: Wednesday, October 19, 2005 4:29 PM
To: TechNet E-Mail Forum; Leo Higgins; [log in to unmask]
Subject: Re: [TN] Delamination at Thermal Via area?
just shooting from the hip but often that large a delam is associated w/
moisture. What's the laminate and what bakes were used in process? W/
this much copper fill can we assume inners have a similar amount of plane
area. If so moisture can't take the short route to the surface and
traditional bakes probably won't be adequate. I'd bet fairly protracted
bakes at each sub as well as final would be appropriate.
dw
At 01:24 PM 10/19/2005, Leo Higgins wrote:
>Hi Steve,
> I have enclosed two photos of a delam between the copper plated over
>the top of a filled via in a double sided PCB substrate for a flip chip
fine
>pitch BGA. Hopefully you can post on your site. The substrate is approx
>200um thick. The vias are not via-in-pad for flip chip solder ball attach.
>The solder balls are attached just adjacent to these filled vias. Via
>filling is insulative. You can see that the vias delaminated at some point
>before the flip chip underfill cured since it is thinner directly over the
>delam area. Since the via fill should be totally encapsulated by copper
due
>to the via sidewall plating and the copper plating over the fill, we
suspect
>the fill was not fully off-gassed and blew its lid with PbFree FC attach.
>Thanks.
>
>
>
>
>Best regards,
>Leo
>
>Director of Applications Engineering
>ASAT, Inc.
>3755 Capital of Texas Highway, Suite 100
>Austin, Texas 78704
>
>ph 512-383-4593
>fx 512-383-1590
>[log in to unmask]
>www.asat.com
>
>
>The information contained in this electronic message is CUSTOMER/SUPPLIER
>PRIVILEGED AND CONFIDENTIAL INFORMATION intended only for the use of the
>individual or entity named above. If the reader of this message is not the
>intended recipient, you are hereby notified that any dissemination,
>distribution and copying of this communication is strictly prohibited. If
>you have received this communication in error, please immediately notify
the
>sender by electronic mail. Thank you.
>
>
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]]On Behalf Of Steve Gregory
>Sent: Wednesday, October 19, 2005 12:49 PM
>To: [log in to unmask]
>Subject: Re: [TN] Delamination at Thermal Via area?
>
>
>Hi George!
>
>Got your pictures up! Check out:
>
>http://www.stevezeva.homestead.com/files/Delamination_Blisters-1.jpg
>http://www.stevezeva.homestead.com/files/Delamination_Blisters-2.jpg
>http://www.stevezeva.homestead.com/files/Delamination_Blisters-3.jpg
>
>Kind regards,
>
>-Steve Gregory-
>Senior Process Engineer
>LaBarge Incorporated
>Tulsa, Oklahoma
>(918) 459-2285
>(918) 459-2350 FAX
>
>
>
>|---------+---------------------------->
>| | "Wenger, George |
>| | M." |
>| | <George.Wenger@an|
>| | drew.com> |
>| | |
>| | 10/19/2005 11:00 |
>| | AM |
>| | |
>|---------+---------------------------->
>
>
>---------------------------------------------------------------------------
>-----------------------------------|
> |
>|
> | To: TechNet E-Mail Forum <[log in to unmask]>@SMTP@Exchange,
>Stephen R Gregory/LABARGE@LABARGE |
> | cc:
>|
> | Subject: RE: [TN] Delamination at Thermal Via area?
>|
>
>
>---------------------------------------------------------------------------
>-----------------------------------|
>
>
>
>Wee Mei,
>
>I've asked Steve to post three images of delamination blistering that
>might be different than you are seeing but the cause is most likely the
>same. I do not know how many layers there are or the number of thermal
>vias there are in the heat spreader portion of the U2 footprint on your
>board but it appears that your delamination is occurring in an area of
>the board where the outside layers are totally covered by metal (i.e.,
>copper). This is decrease the ability of the board to outgas in those
>areas if the board is heated too rapidly or to too high a temperature.
>I'm also assuming but can't tell because I haven't seen a cross section
>of your thermal vias but my guess would be that you do not have good
>attachment integrity of the outer-layer copper to the barrels of the
>thermal vias and therefore the thermal vias are not providing any
>mechanical strength to hole you board together when reflowed. The three
>images I've sent to Steve show delamination blisters on the bottom side
>of a 14-Layer PCB. The delamination is occurring between layer 13 and
>layer 14 in areas that have a copper ground plane on Layer 14. There
>acre also not PTH's in these areas to hold the board together when
>internal moisture is driven off too fast. There are no blisters where
>ever there are PTH's. We're not sure there was a single cause for our
>delamination or multiple causes. These boards were over 1 year old and
>could have and probably did absorb moisture from the environment. We
>believe the reflow profile that caused these blisters had too fast a
>ramp and too hot a peak temperature. If we baked the boards prior to
>the reflow they didn't delamination or if we didn't bake the boards and
>used a correct profile they didn't blister. I hope this information
>helps you find the root cause for you delamination. My suggestion is to
>examine your reflow profile and cross section thermal vias in the
>blistered area.
>
>
>Regards,
>George
>George M. Wenger
>Reliability / FMA Engineer
>Base Station and Subsystems Group
>Andrew Corporation, 40 Technology Drive, Warren, NJ 07059 (908) 546-4531
>[log in to unmask]
>
>-----Original Message-----
>From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
>Sent: Wednesday, October 19, 2005 10:30 AM
>To: [log in to unmask]
>Subject: Re: [TN] Delamination at Thermal Via area?
>
>Hi Wee Mei!
>
>I've got your pictures posted. Go to:
>
>http://www.stevezeva.homestead.com/files/U2_top.JPG
>http://www.stevezeva.homestead.com/files/U2_bottom.JPG
>http://www.stevezeva.homestead.com/files/U2_delamination.JPG
>
>Are the vias filled? Are you seeing this delamination on very many
>PCB's? Are you seeing it only on the bottom of the PCB?
>
>Kind regards,
>
>-Steve Gregory-
>Senior Process Engineer
>LaBarge Incorporated
>Tulsa, Oklahoma
>(918) 459-2285
>(918) 459-2350 FAX
>
>
>
>|---------+---------------------------->
>| | Wee Mei |
>| | <[log in to unmask]
>| | SG> |
>| | Sent by: TechNet |
>| | <[log in to unmask]>|
>| | |
>| | |
>| | 10/19/2005 03:47 |
>| | AM |
>| | Please respond to|
>| | TechNet E-Mail |
>| | Forum |
>| | <[log in to unmask]>|
>| | ; Please respond |
>| | to Wee Mei |
>| | <[log in to unmask]
>| | SG> |
>| | |
>|---------+---------------------------->
>
> >-----------------------------------------------------------------------
>---------------------------------------|
> |
>|
> | To: [log in to unmask]@SMTP@Exchange
>|
> | cc: (bcc: Stephen R Gregory/LABARGE)
>|
> | Subject: [TN] Delamination at Thermal Via area?
>|
>
> >-----------------------------------------------------------------------
>---------------------------------------|
>
>
>
>Hello,
>
>Just asked Steve to download 3 pictures on the defects. Kindly take a
>look at them and would appreciate some feedback on the possible root
>cause.
>
>Steve : Thanks for the downloading.
>
>Regards,
>Wee Mei
>
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